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Method for fabricating semiconductor deviceRelated Patent Categories: Semiconductor Device Manufacturing: Process, Coating With Electrically Or Thermally Conductive Material, To Form Ohmic Contact To Semiconductive Material, Contacting Multiple Semiconductive Regions (i.e., Interconnects), Multiple Metal Levels, Separated By Insulating Layer (i.e., Multiple Level Metallization), With Formation Of Opening (i.e., Viahole) In Insulative Layer, Having Viaholes Of Diverse WidthMethod for fabricating semiconductor device description/claimsThe Patent Description & Claims data below is from USPTO Patent Application 20070042600, Method for fabricating semiconductor device. Brief Patent Description - Full Patent Description - Patent Application Claims
BACKGROUND OF THE INVENTION [0001] (a) Fields of the Invention [0002] The present invention relates to methods for fabricating a semiconductor device, and in particular to interconnect formation processes using an insulating-layer formation material and a metal material serving as an interconnect layer. [0003] (b) Description of Related Art [0004] With shrinking design rules of semiconductor devices, circuit integration in the devices dramatically increases, so that more than one hundred million transistors can be provided on one chip. To provide such a chip, not only microfabrication technologies such as lithography and etching are developed which require a processing accuracy of the order of several tens of nanometers, but also lowered resistance of interconnects, lowered dielectric constant of interlayer insulating films, and multi-layer interconnection are needed. [0005] A method for forming an interconnect of a semiconductor device using a low dielectric constant insulating material (referred hereinafter to as a low-k material) includes, for example, a Cu dual-damacene technique (see Japanese Unexamined Patent Publication No. 2003-23072). Hereinafter, a formation process of Cu dual-damacene interconnects will be described according to views of process steps in FIG. 4. FIGS. 4A to 4O are sectional views showing conventional interconnect formation steps. [0006] A first description will be made of a formation method of an interlayer insulating film. Referring to FIGS. 4A and 4B, a barrier metal 102 and a copper interconnect layer 103 are formed which are buried in a first low-dielectric-constant interlayer film (referred hereinafter to as a first low-k interlayer film) 101. Subsequently, over a substrate, a liner film 104 of, for example, SiCN is formed by a plasma CVD method. Then, as shown in FIG. 4C, a second low-dielectric-constant interlayer film (referred hereinafter to as a second low-k interlayer film) 105 of, for example, SiOC is deposited on the liner film 104. As shown in FIG. 4D, using a chemical mechanical polishing method (referred hereinafter to as a CMP method), the second low-k interlayer film 105 is polished to have a predetermined thickness. Thereafter, as shown in FIG. 4E, a cap layer 106 of a silicon oxide film formed by a plasma CVD method is deposited on the second low-k interlayer film 105. [0007] Next, the low-k interlayer film 105 and the cap layer 106 formed by the procedure shown above are subjected to patterning using a lithography technology and a dry etching technology. First, as shown in FIG. 4F, a photoresist film 107 is applied over the top surface of the substrate, and patterning by a lithography technology is conducted to form a hole-shaped opening through the photoresist film 107. Then, as shown in FIG. 4G, using the resulting photoresist film 107 as a mask, the cap layer 106 and the second low-k interlayer film 105 are dry etched to form a hole-shaped opening (a via hole). As shown in FIGS. 4H and 4I, the photoresist film 107 and a polymer or the like generated during the etching are removed, and then the via hole is filled with a photoresist to form a photoresist filling layer 108. Thereafter, as shown in FIG. 4J, a photoresist film 109 is applied to the substrate, and using a lithography technology, the photoresist film 109 is formed with a groove-shaped opening. As shown in FIG. 4K, using the resulting photoresist film 109 as a mask, the cap layer 106 and the second low-k interlayer film 105 are dry etched to form a groove-shaped opening, and then the photoresist film 109 and the photoresist filling layer 108 are removed. Subsequently, as shown in FIG. 4L, using an etch back method, a portion of the liner film 104 located on the copper interconnect layer 103 is removed to form an opened portion. During this removal, the cap layer 106 is also removed by the etch back. [0008] Next, an interconnect layer is formed in the interlayer insulating film with the opening formed therein. First, as shown in FIG. 4M, by a sputtering method, a barrier metal 110 is deposited which is made of, for example, a stacked film of Ta and TaN. As shown in FIG. 4N, a Cu seed layer is formed by a sputtering method, and on this layer, copper is deposited by a plating method to form a copper film 111. Thereafter, a portion of the copper film 111 adhering to a wafer edge is wet etched. As shown in FIG. 4O, unnecessary portions of the barrier metal 110 and the copper film 111 are removed by a CMP method (Cu-CMP) to form an interconnect layer in the insulating film. [0009] Through the process steps described above, an interconnect layer of a single layer is formed. By repeatedly conducting the steps shown in FIGS. 4A to 4O, multilayer interconnects can be fabricated. SUMMARY OF THE INVENTION [0010] When the interconnect layer is formed by the above process steps, however, delamination from the edge of the wafer occurs to affect the yield of the device. The term "the edge of a wafer (or a wafer edge)" in this description means a region of a wafer located outside a chip formation region (semiconductor element formation region), while the term "a bevel (or a wafer bevel)" means a portion of a wafer contained in the wafer edge and having the surface inclined relative to the plane of the chip formation region. Following wafer size enlargement, the ratio of the number of chips on the wafer outer region to the total number of chips on the wafer increases, so that delamination from the edge becomes unacceptable. In addition, as the number of interconnect layers increases, delamination from the edge is facilitated. This obstructs development of multi-layer interconnection. [0011] FIGS. 5A to 5D are schematic views showing cross-sectional structures of a wafer edge in the case where interconnect layers are formed by the conventional method. These figures illustrate an example in which a first low-k interlayer film 122, a liner film 123, a second low-k interlayer film 125, and a barrier metal 124 are deposited on a semiconductor substrate 121. [0012] FIG. 5A shows the overall view of the wafer edge. The state of the wafer cross section can be separated into: the top surface of the wafer bevel (a region 1); the side surface of the wafer bevel (a region 2); the back surface of the wafer bevel (a region 3); and the back surface of the wafer edge (a region 4). The region 1 has a stacked structure in which the low-k interlayer film, the liner film, and the barrier metal are smooth, respectively. [0013] FIG. 5B is an enlarged schematic view of the wafer cross section in the region 2. In the region 2, the first low-k interlayer film 122 and the second low-k interlayer film 125 with upward-pointed parts are observed on the semiconductor substrate 121. Also, the region 2 is dotted with the barrier metal layers 124 formed to come onto the wafer side surface during film formation by a sputtering. [0014] FIG. 5C is an enlarged schematic view of the wafer cross section in the region 3. The top of the semiconductor substrate 121 and the first low-k interlayer film 122 are dotted with the barrier metal layers 124 formed to come onto the wafer back surface during film formation by a sputtering. Also, the second low-k interlayer film 125 is deposited unevenly. In particular, some portions of the film 125 located around the barrier metal 124 are extremely thin. [0015] FIG. 5D is an enlarged schematic view of the wafer cross section in the region 4. The top of the semiconductor substrate 121 is dotted with the barrier metals 124 formed to come onto the wafer back surface during film formation by a sputtering. [0016] As is apparent from FIGS. 5A to 5D, when the interconnect layers are formed using the currently-used flow, the wafer edge becomes extremely rough and a number of portions that will serve as points of initiation of delamination are present in the edge. [0017] An object of the present invention is to provide a method for fabricating a semiconductor device which can suppress delamination from a wafer edge by taking measures against the above problems. [0018] A method for fabricating a semiconductor device according to the present invention comprises: the step (a) of forming an insulating film over the top surface of a wafer-shaped semiconductor substrate; the step (b) of forming a protective film over the side and back surfaces of the semiconductor substrate including the insulating film; the step (c) of removing a portion of the protective film located above a chip formation region of the semiconductor substrate to leave at least a portion of the protective film located on an exposed surface of a wafer bevel of the semiconductor substrate; the step (d) of etching, after the step (c), a portion of the insulating film to form an opening in the insulating film; the step (e) of sequentially forming, after the step (d), a barrier film and a metal film in this order over the top surface of the semiconductor substrate; the step (f) of removing the protective film after the step (e); and the step (g) of removing, after the step (f), portions of the metal film and the barrier film provided on the insulating film to form a metal interconnect filling the opening. [0019] With this method, the protective film can be provided to prevent a portion of the insulating film over the side surface of the wafer bevel from being damaged during the etching (particularly dry etching) in the step (d), so that the surface of the insulating film after formation of the interconnect can be kept in a smooth condition. Furthermore, the material of the interconnect such as the barrier metal can also be prevented from coming onto the back surface of the bevel. This suppresses delamination from the wafer edge including the bevel, so that the yields of the semiconductor devices fabricated around the wafer edge can be improved. [0020] The steps (c) and (f) can be conducted by, for example, a spin etching or the like with a chemical solution selectively dissolving the protective film. In these steps, inert gas such as nitrogen may be sprayed on a surface that is not wished to be etched. [0021] In the step (c), by a CMP method, the protective film and the insulating film can be polished and removed in the same step. With this method, the number of process steps can be reduced and concurrently the protective film and the insulating film do not have to be made of materials having etching selectivities with respect to each other. [0022] The insulating film may be made of, for example, an organic-based low-dielectric-constant material such as SiOC. Continue reading about Method for fabricating semiconductor device... Full patent description for Method for fabricating semiconductor device Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Method for fabricating semiconductor device patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. Start now! - Receive info on patent apps like Method for fabricating semiconductor device or other areas of interest. ### Previous Patent Application: Dielectric with sidewall passivating layer Next Patent Application: Methods to facilitate etch uniformity and selectivity Industry Class: Semiconductor device manufacturing: process ### FreshPatents.com Support Thank you for viewing the Method for fabricating semiconductor device patent info. IP-related news and info Results in 2.1356 seconds Other interesting Feshpatents.com categories: Daimler Chrysler , DirecTV , Exxonmobil Chemical Company , Goodyear , Intel , Kyocera Wireless , 174 |
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