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  Method for fabricating multi-chip semiconductor packageUSPTO Application #: 20070249094Title: Method for fabricating multi-chip semiconductor package Abstract: A multi-chip semiconductor package and a fabrication method thereof are provided. At least one first chip is mounted on and electrically connected to an upper surface of a substrate via solder bumps. A preformed package structure having a second chip and a first encapsulation body is mounted on the upper surface of the substrate, wherein outer leads of the preformed package structure are exposed from the first encapsulation body and electrically connected to the upper surface of the substrate. The first encapsulation body, outer leads and substrate form a space where the first chip is received, and a gap is present between the first chip and the first encapsulation body. A second encapsulation body is formed on the upper surface of the substrate to encapsulate the first chip, solder bumps and preformed package structure. A plurality of solder balls are implanted on the lower surface of the substrate. (end of abstract) Agent: Edwards Angell Palmer & Dodge LLP - Boston, MA, US Inventor: Han-Ping Pu USPTO Applicaton #: 20070249094 - Class: 438109000 (USPTO) Related Patent Categories: Semiconductor Device Manufacturing: Process, Packaging (e.g., With Mounting, Encapsulating, Etc.) Or Treatment Of Packaged Semiconductor, Assembly Of Plural Semiconductive Substrates Each Possessing Electrical Device, Stacked Array (e.g., Rectifier, Etc.) The Patent Description & Claims data below is from USPTO Patent Application 20070249094. Brief Patent Description - Full Patent Description - Patent Application Claims
FIELD OF THE INVENTION [0001] The present invention relates to multi-chip semiconductor packages and fabrication methods thereof, and more particularly, to a multi-chip semiconductor package with a packaged chip and a flip chip being incorporated on a substrate, and a method of fabricating the semiconductor package. BACKGROUND OF THE INVENTION [0002] In accordance with electronic products being developed with compact size, light weight and high efficiency, semiconductor packages have been correspondingly reduced in profile and preferably incorporated with multiple chips to be suitable for use with the electronic products. Such structure with multiple semiconductor chips being mounted in a single package is customarily referred to as a multi-chip semiconductor package, wherein the multiple chips can be vertically stacked on a chip carrier (such as a substrate or lead frame) or individually attached to the substrate. The multi-chip package structure has a primary advantage for providing the semiconductor package with effectively enhanced or multiplied electrical and operational performances, making it suitably used in the highly efficient electronic product. [0003] U.S. Pat. Nos. 5,696,031 and 5,973,403 have disclosed a multi-chip semiconductor package. Referring to FIG. 5, in this semiconductor package, a first chip 21 is mounted on a surface of a substrate 20 in a flip-chip manner that an active surface 210 of the first chip 21 faces downwards and is electrically connected to the substrate 20 via a plurality of solder bumps 22. Then, a second chip 23 is attached to a non-active surface 211 of the first chip 21 and is electrically connected to the substrate 20 via a plurality of bonding wires 24. An encapsulation body 25 is formed on the substrate 20 to encapsulate the first chip 21, second chip 23 and bonding wires 24. Finally, a plurality of solder balls 26 are implanted on an opposite surface of the substrate 20. This completes fabrication of the multi-chip semiconductor package. Since the wire-bonding process performed on the second chip 23 would generate shocks that may cause cracks of the solder bumps 22, an underfill process is carried out between the first chip 21 and the substrate 20 to fill an insulating material (such as a resin material, etc.) in gaps between the adjacent solder bumps 22, so as to enhance the mechanical strength of the solder bumps 22 and prevent them from cracks due to the shocks generated by the wire-bonding process. [0004] However, during the underfill process for the above semiconductor package, the procedure of filling the insulating material may easily contaminate predetermined positions (such as bond fingers) on the substrate for connecting the bonding wires, and the bonding wires cannot be fly bonded to the contaminated bond fingers, such that the yield of the wire-bonding process and the quality of electrical connection between the second chip and the substrate would be degraded, and the reliability of the entire semiconductor package is thus deteriorated. Moreover, for the second chip that is electrically connected to the substrate via the bonding wires, since the second chip is directly incorporated in the semiconductor package with the quality and yield of the second chip being unknown, a known good die (KGD) issue is produced. In other words, if the second chip not passing a burn-in test incurs quality defects, the entire package having such second chip would fail and the product yield is reduced. [0005] U.S. Patent Publication No. 2004/0113275 has disclosed another multi-chip semiconductor package. As shown in FIG. 6, this semiconductor package allows a first chip 31 to be mounted on a surface of a substrate 30 in a flip-chip manner, wherein an active surface 310 of the first chip 31 faces downwards and is electrically connected to the substrate 30 via a plurality of solder bumps 32. An insulating material (such as a resin material, etc.) is filled in gaps between the adjacent solder bumps 32 using an underfill technique. Then, a land grid array (LGA) package structure 33 is attached to a non-active surface 311 of the first chip 31 in an inverted manner, and a substrate 330 of the LGA package structure 33 is electrically connected to the substrate 30 via a plurality of bonding wires 34. An encapsulation body 35 is formed on the substrate 30 to encapsulate the first chip 31, LGA package structure 33 and bonding wires 34. Finally, a plurality of solder balls 36 are implanted on an opposite surface of the substrate 30. This completes fabrication of the multi-chip semiconductor package. [0006] Although the above fabrication method may solve the KGD problem, the multi-chip semiconductor package shown in FIG. 6 still have the similar drawback to that shown in FIG. 5. As the underfill process is required to fill the gaps between the adjacent solder bumps 32 with the insulating material so as to enhance the mechanical strength of the solder bumps 32 and prevent them from cracks due to shocks during the wire-bonding process, the procedure of filling the insulating material may easily contaminate predetermined positions (such as bond fingers) on the substrate 30 for connecting the bonding wires 34, and the bonding wires 34 cannot be firmly bonded to the contaminated bond fingers, thereby degrading the yield of the wire-bonding process and the quality of electrical connection between the LGA package structure 33 and the substrate 30, as well as deteriorating the reliability of the entire semiconductor package. [0007] Therefore, the problem to be solved here is to provide a multi-chip semiconductor package, which can prevent predetermined positions for electrical connection on a substrate from contamination and eliminate a KGD issue so as to assure the reliability and yield of the semiconductor package. SUMMARY OF THE INVENTION [0008] In light of the above drawbacks in the prior art, an objective of the present invention is to provide a multi-chip semiconductor package and a fabrication method thereof, which do not require an underfill process, such that predetermined positions for electrical connection on a substrate can be prevented from contamination, and the electrical connection quality and reliability of the semiconductor package are assured. [0009] Another objective of the present invention is to provide a multi-chip semiconductor package and a fabrication method thereof, wherein a preformed package structure passing a burn-in test is incorporated in the semiconductor package, such that a known good die (KGD) issue can be eliminated, and the reliability and yield of the semiconductor package are assured. [0010] A further objective of the present invention is to provide a multi-chip semiconductor package and a fabrication method thereof, with a thermally conductive adhesive being applied between an upper packaged chip and a lower flip chip in the semiconductor package, such that heat generated by the upper chip can be transmitted to the lower chip and then to a substrate to be dissipated out of the semiconductor package, thereby effectively improving the heat dissipating efficiency of the semiconductor package. [0011] In accordance with the above and other objectives, the present invention proposes a multi-chip semiconductor package, comprising a substrate having an upper surface and a lower surface opposed to the upper surface; at least one first chip having an active surface and a non-active surface, wherein the active surface of the first chip is mounted on and electrically connected to the upper surface of the substrate via a plurality of solder bumps; a preformed package structure comprising a lead frame, at least one second chip mounted on and electrically connected to the lead frame, and a first encapsulation body for encapsulating the second chip and a portion of the lead frame, wherein outer leads of the lead frame are exposed from the first encapsulation body and mounted on the upper surface of the substrate, such that the first encapsulation body, the exposed outer leads and the substrate form a space where the first chip is received, and a gap is present between the non-active surface of the first chip and the first encapsulation body; a second encapsulation body formed on the upper surface of the substrate to encapsulate the first chip, the solder bumps and the preformed package structure; and a plurality of solder balls implanted on the lower surface of the substrate. The present invention also proposes a fabrication method of the above multi-chip semiconductor package, comprising the steps of: preparing a substrate having an upper surface and a lower surface opposed to the upper surface; providing at least one first chip having an active surface and a non-active surface, and allowing the active surface of the first chip to be mounted on and electrically connected to the upper surface of the substrate via a plurality of solder bumps; mounting a preformed package structure on the upper surface of the substrate, the preformed package structure comprising a lead frame, at least one second chip mounted on and electrically connected to the lead frame, and a first encapsulation body for encapsulating the second chip and a portion of the lead frame, wherein outer leads of the lead frame are exposed from the first encapsulation body and mounted on the upper surface of the substrate, such that the first encapsulation body, the exposed outer leads and the substrate form a space where the first chip is received, and a gap is present between the non-active surface of the first chip and the first encapsulation body; forming a second encapsulation body on the upper surface of the substrate to encapsulate the first chip, the solder bumps and the preformed package structure; and implanting a plurality of solder balls on the lower surface of the substrate. [0012] The above multi-chip semiconductor package can also be fabricated by a batch method comprising the steps of: providing a substrate strip comprising a plurality of substrates and having an upper surface and a lower surface opposed to the upper surface; mounting at least one first chip on the upper surface of each of the substrates, the first chip having an active surface and a non-active surface, and allowing the active surface of the first chip to be mounted on and electrically connected to the upper surface of each of the substrates via a plurality of solder bumps; mounting a preformed package structure on the upper surface of each of the substrates, the preformed package structure comprising a lead frame, at least one second chip mounted on and electrically connected to the lead frame, and a first encapsulation body for encapsulating the second chip and a portion of the lead frame, wherein outer leads of the lead frame are exposed from the first encapsulation body and mounted on the upper surface of each of the substrates, such that the first encapsulation body, the exposed outer leads and the corresponding substrate form a space where the first chip is received, and a gap is present between the non-active surface of the first chip and the first encapsulation body; forming a second encapsulation body on the upper surface of the substrate strip to encapsulate all of the first chips, the solder bumps and the preformed package structures; implanting a plurality of solder balls on the lower surface of the substrate strip; and performing a singulation process to cut the second encapsulation body and the substrate strip so as to separate apart the plurality of substrates and form a plurality of individual semiconductor packages. [0013] The second chip in the preformed package structure is electrically connected to the lead frame via a plurality of bonding wires. The lead frame comprises a die pad and a plurality of leads, wherein each of the leads is composed of an inner lead and an outer lead. The second chip is mounted on an upper surface of the die pad and electrically connected to the inner leads. The inner leads and the bonding wires are encapsulated by the first encapsulation body. In one preferred embodiment, the die pad is encapsulated by the first encapsulation body, and the gap between the first chip and the first encapsulation body is filled with the second encapsulation body. In another preferred embodiment, a lower surface of the die pad is exposed from the first encapsulation body and abuts against the gap between the first chip and the first encapsulation body, such that a thermally conductive adhesive is filled in the gap between the first chip and the first encapsulation body prior to fabrication of the second encapsulation body. [0014] The above multi-chip semiconductor package and its fabrication methods allow a substrate to accommodate both a packaged chip and a flip chip. This is accomplished by firstly, electrically connecting a first chip in a flip-chip manner to the substrate via a plurality of solder bumps, and then mounting a preformed package structure on the substrate, wherein the preformed package structure is incorporated with a second chip and has exposed outer leads that are mounted and electrically connected to the substrate by surface mount technology (SMT), such that a first encapsulation body of the preformed package structure, the exposed outer leads and the substrate form a space where the first chip is received, and the first encapsulation body is supported above the first chip, with a gap being present between the first encapsulation body and the first chip. Since the preformed package structure is electrically connected to the substrate by the surface mount technology, the solder bumps located between the first chip and the substrate would not subject to cracks caused by shocks generated during a wire-bonding process in the prior art. Thus, an underfill process is not required in the present invention to fill gaps between the adjacent solder bumps located between the first chip and the substrate. On the other hand, in the present invention, a single molding process is carried out to form a second encapsulation body for encapsulating the first chip and the preformed package structure as well as filling the gap between the first encapsulation body and the first chip and the gaps between the adjacent solder bumps. This can prevent predetermined positions on the substrate for mounting the outer leads of the preformed package structure from contamination by the underfill process, and assure the preformed package structure to be well mounted and electrically connected to the substrate, such that the electrical connection quality and reliability of the entire semiconductor package would not be affected. Moreover, the fabricated preformed package structure before being mounted on the substrate is subjected to a burn-in test. Specifically, only the preformed package structure that has successfully passed the burn-in test would be mounted on the substrate. As a result, the preformed package structure would not contain a second chip that is defective or unknown with its quality, such that the conventional known good die (KGD) problem can be eliminated, and the reliability and yield of the entire semiconductor package are assured. Additionally, in another preferred embodiment of the present invention, a lead frame of the preformed package structure has a die pad exposed from the first encapsulation body, with a lower surface of the die pad abutting against the gap between the first encapsulation body and the first chip, and prior to fabricating the second encapsulation body, a thermally conductive adhesive is applied in the gap between the first encapsulation body and the first chip, such that heat generated by the second chip mounted on the die pad can be transmitted via the die pad and the thermally conductive adhesive to the first chip and then transmitted via the solder bumps and the substrate to be dissipated out of the semiconductor package. This thus effectively improves the heat dissipating efficiency of the entire semiconductor package. Furthermore, the semiconductor package in the present invention has a multi-chip structure containing at least the first and second chips, thereby providing the entire semiconductor package with enhanced electrical and operational performances. BRIEF DESCRIPTION OF THE DRAWINGS [0015] The present invention can be more fully understood by reading the following detailed description of the preferred embodiments, with reference made to the accompanying drawings, wherein: [0016] FIG. 1 is a cross-sectional view of a multi-chip semiconductor package according to a first preferred embodiment of the present invention; [0017] FIGS. 2A to 2E are schematic diagrams showing a set of steps of fabricating the semiconductor package in FIG. 1; [0018] FIGS. 3A to 3F are schematic diagrams showing another set of steps of fabricating the semiconductor package in FIG. 1; [0019] FIG. 4 is a cross-sectional view of a multi-chip semiconductor package according to a second preferred embodiment of the present invention; [0020] FIG. 5 (PRIOR ART) is a cross-sectional view of a conventional multi-chip semiconductor package; and Continue reading... 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