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  Method for fabricating a semiconductor deviceUSPTO Application #: 20060194400Title: Method for fabricating a semiconductor device Abstract: A method for fabricating a semiconductor device includes forming a first semiconductor layer on a front side of the semiconductor substrate. Additional semiconductor layers may be formed on a font side of the first semiconductor layer. The substrate is subsequently removed. In some embodiments, one or more additional semiconductor layers may be formed on the back side of the first semiconductor layer after the semiconductor substrate has been removed. Additionally, in some embodiments, a portion of the first semiconductor layer is removed along with the semiconductor substrate. In such embodiments, the first semiconductor layer is subsequently etched to a known thickness. Source regions and device electrodes may be then be formed. (end of abstract) Agent: Barnes & Thornburg - Indianapolis, IN, US Inventors: James A. Cooper, Xiaokun Wang USPTO Applicaton #: 20060194400 - Class: 438309000 (USPTO) Related Patent Categories: Semiconductor Device Manufacturing: Process, Forming Bipolar Transistor By Formation Or Alteration Of Semiconductive Active Regions The Patent Description & Claims data below is from USPTO Patent Application 20060194400. Brief Patent Description - Full Patent Description - Patent Application Claims
[0001] This patent application claims priority to and the benefit of U.S. Provisional Patent Application Ser. No. 60/646,151 entitled "High-Voltage N-Channel Insulated Gate Bipolar Transistor (IGBT) in Silicon Carbide" which was filed on Jan. 21, 2005, the entirety of which is expressly incorporated herein by reference. TECHNICAL FIELD [0002] The present disclosure relates generally to methods for fabricating semiconductor devices, and more particularly to methods for fabricating high-power semiconductor devices. BACKGROUND [0003] High-power semiconductor devices, such as insulated-gate bipolar transistors, are typically fabricated on thick substrates to, for example, provide sufficient structural support for the semiconductor device during the fabrication process. In some applications, the thick substrates may present a high parasitic series resistance in the device due to carrier freeze-out and/or low hole mobility in the substrate. SUMMARY [0004] A method for fabricating a semiconductor device may include forming a semiconductor substrate. The semiconductor substrate may be, for example, a silicon-carbide semiconductor substrate. The method may also include forming a first semiconductor layer on a front side of the semiconductor substrate. The first semiconductor layer may be so formed by, for example, epitaxially growing the first semiconductor layer. The first semiconductor layer may be formed on either a silicon side or a carbon side of the semiconductor substrate. The first semiconductor layer may be, for example, a drift semiconductor layer. The drift semiconductor layer may have a first concentration of first type impurities that is less than a second concentration of first type impurities of the semiconductor substrate. Alternatively, the semiconductor substrate may be doped with second type impurities. The first semiconductor layer may be formed to a thickness of about one micrometer. The method also includes removing the semiconductor substrate after the formation of the first semiconductor layer. The semiconductor layer may be so removed by using, for example, a chemical mechanical polishing process. Removing the substrate may include removing a portion of the first semiconductor layer. The semiconductor device may be an insulated-gate bipolar transistor. For example, the semiconductor device may be a DMOS insulated-gate bipolar transistor or a UMOS insulated-gate bipolar transistor. [0005] The method may also include forming a second semiconductor layer on a front side of the first semiconductor layer. The first semiconductor layer may have a first concentration of first type impurities and the second semiconductor layer may have a second concentration of second type impurities. The method may also include forming a second semiconductor layer on a back side of the first semiconductor layer after the semiconductor substrate has been removed. The first semiconductor layer may form a bottom semiconductor layer or a top semiconductor layer of the device after the semiconductor substrate has been removed. Removing the substrate may include removing a portion of the first semiconductor layer. [0006] The method may further include determining a thickness of the first semiconductor layer subsequent to the removing step. The thickness of the first semiconductor layer may be determined, for example, by use of a trench length measure process. For example, the thickness of the first semiconductor layer may be determined, subsequent to the removing step, based on a sheet resistivity of the first semiconductor layer. Determining the thickness of the first semiconductor layer may also include extrapolating a conductivity of the first semiconductor layer to a value of about zero. The first semiconductor layer may then be etched to a known thickness based on the determined thickness. [0007] A method for fabricating an insulated-gate bipolar transistor may include forming a semiconductor substrate. The semiconductor substrate may be, for example, a silicon-carbide semiconductor substrate. The method may also include forming a drift semiconductor layer on a front side of the semiconductor substrate. The drift semiconductor layer may be so formed by, for example, epitaxially growing the drift semiconductor layer on the semiconductor substrate. The drift semiconductor layer may be formed on a silicon side or a carbon side of the semiconductor substrate. The method also includes forming a drain layer on a front side of the drift semiconductor layer. The drift semiconductor layer may be doped with first type impurities while the drain semiconductor layer may be doped with second type impurities. The method may further include forming a first source region and a second source region in the drift semiconductor layer. The first and second source regions may be formed in the drift semiconductor layer subsequent to the removing step. The method may yet further include forming a first source contact on a front side of the first source region and a second source contact on a front side of the second source region. The method may include forming a gate oxide on a back side of the first semiconductor layer and a gate contact on a front side of the gate oxide. The method may also include forming a drain contact on a front side of the drain semiconductor layer. The method may yet further include forming an additional semiconductor layer on a back side of the drift semiconductor layer subsequent to the removing step. [0008] A method for fabricating an insulated-gate bipolar transistor may include forming a semiconductor substrate, which may be formed from a silicon-carbide material. The method may also include forming a first semiconductor layer on a front side of the first semiconductor substrate. The method may also include forming a second semiconductor layer on a front side of the first semiconductor layer. The method may yet further include removing the semiconductor substrate and a portion of the first semiconductor layer. The method may also include forming a third semiconductor layer on a front side of the second semiconductor layer. The method may also include determining a thickness of the first semiconductor layer subsequent to the removing step. The thickness of the first semiconductor layer may be determined by, for example, use of a trench length measure technique. Additionally, the thickness of the first semiconductor layer may be determined based on a sheet resistivity of the first semiconductor layer. Determining the thickness of the first semiconductor layer subsequently to the removing step may also include extrapolating a conductivity of the first semiconductor layer to a value of about zero. [0009] A method for fabricating a semiconductor device on a semiconductor substrate may include forming a first semiconductor layer on a front side of the semiconductor substrate. The method may also include forming a second semiconductor layer on a front side of the first semiconductor layer. The first and the second semiconductor layers may be formed from a silicon-carbide material. The method may further include removing the semiconductor substrate. Additionally, the method may yet further include processing the semiconductor device after the removing step to form an insulated-gate bipolar transistor. [0010] The above and other features of the present disclosure, which alone or in any combination may comprise patentable subject matter, will become apparent from the following description and the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS [0011] The detailed description particularly refers to the following figures, in which: [0012] FIG. 1 is a flowchart of one embodiment of an algorithm for fabricating a semiconductor device; [0013] FIGS. 2a-2f are fragmentary, cross-sectional views of one embodiment of a semiconductor device at different stages of fabrication according to the algorithm of FIG. 1; [0014] FIG. 3 is a flowchart of another embodiment of a sub-process of the algorithm for fabricating a semiconductor device of FIG. 1; [0015] FIGS. 4a-4d are fragmentary, cross-sectional views of one embodiment of a semiconductor device at different stages of fabrication according to the algorithm of FIGS. 1 and 3; [0016] FIG. 5 is a flowchart of another embodiment of an algorithm for fabricating a semiconductor device; [0017] FIG. 6 is a flowchart of one embodiment of an algorithm for determining a thickness of a semiconductor layer used in the algorithm of FIG. 5; [0018] FIG. 7 is a fragmentary, cross-sectional view of one embodiment of a semiconductor device fabricated using the algorithm of FIG. 5; [0019] FIGS. 8a-8b are views of a test area created during the execution of the algorithm of FIG. 6; [0020] FIG. 9 is a graph showing a theoretical relationship between the conductivity and etching depth of a semiconductor wafer used in the algorithm of FIG. 6; Continue reading... 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