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Method for designing semiconductor package, system for aiding to design semiconductor package, and computer program product thereforMethod for designing semiconductor package, system for aiding to design semiconductor package, and computer program product therefor description/claimsThe Patent Description & Claims data below is from USPTO Patent Application 20070204251, Method for designing semiconductor package, system for aiding to design semiconductor package, and computer program product therefor. Brief Patent Description - Full Patent Description - Patent Application Claims
BACKGROUND OF THE INVENTION [0001]This invention relates to a designing method aiming power integrity of a semiconductor chip included in a semiconductor package and to a design aid system and a computer program product in both of which the method is implemented. [0002]In a semiconductor chip such as a dynamic random access memory (DRAM) chip, transient currents flow through a power supply pad and a ground pad of the semiconductor chip, for example, when an output driver of the semiconductor chip changes its output state, i.e. from high level to low level, or from low level to high level. The transient currents cause voltage fluctuations at the power supply pad and the ground pad. [0003]If the above-mentioned voltage fluctuations exceed a certain level, the semiconductor chip fails to function properly. Therefore, a semiconductor package should be designed so that the above-mentioned voltage fluctuations do not exceed the voltage fluctuation limitation. [0004]In order to verify whether voltage fluctuations are allowable, a transient analysis with a SPICE (Simulation Program with Integrated Circuit Emphasis) model is conventionally carried out as disclosed in JP-A 2004-54522. When a user finds out as a result of the conventional transient analysis that a designed semiconductor package violates the voltage fluctuation limitation therefor, the user should carry out design modification such as layout modification on the previously-designed package and then carry out a transient analysis on a newly-designed package, again. Normally, the above-mentioned analysis and design modification is carried out multiple times by trial and error, in accordance with the conventional transient analysis, so that its design cycle needs long time. [0005]JP-A 2005-198406 has proposed another approach. The disclosed approach includes an analysis not in time domain but in frequency domain; the analysis is carried out on a fine layout to be formed on a semiconductor chip. However, the disclosed analysis cannot be carried out on a semiconductor package that comprises an already-designed semiconductor chip. SUMMARY OF THE INVENTION [0006]It is an object of the present invention to provide a novel design method which can shorten a design cycle of a semiconductor package even if the semiconductor package comprises an already-designed semiconductor chip. [0007]One aspect of the present invention provides a method for designing a semiconductor package which comprises a semiconductor chip and an adjustment target. The method according to one aspect of the present invention comprises: calculating a first target variable on the basis of a first chip model and a target impedance model, the first chip model being created by representing the semiconductor chip in frequency domain in consideration of a first transition state, the first transition state being a state where an output level of the semiconductor chip changes from a low level to a high level, the target impedance model being assumed by representing the adjustment target in frequency domain; calculating a second target variable on the basis of a second chip model and the target impedance model, the second chip model being created by representing the semiconductor chip in frequency domain in consideration of a second transition state, the second transition state being a state where an output level of the semiconductor chip changes from the high level to the low level; in consideration of power integrity for the semiconductor chip, selecting inferior one of the first and the second target variables as a main target variable; and comparing the main target variable and a predetermined constraint represented in frequency domain to decide design guidelines for the adjustment target. [0008]An appreciation of the objectives of the present invention and a more complete understanding of its structure may be had by studying the following description of the preferred embodiment and by referring to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS [0009]FIG. 1 is a view showing a semiconductor package which has an adjustment target on design in accordance with a first embodiment of the present invention: [0010]FIG. 2 is a view showing a general model of the semiconductor package of FIG. 1; [0011]FIG. 3 is a view showing a first chip model for power supply voltage fluctuation; [0012]FIG. 4 is a view showing a first chip model for ground voltage fluctuation; [0013]FIG. 5 is a view showing a second chip model for power supply voltage fluctuation; [0014]FIG. 6 is a view showing a second chip model for ground voltage fluctuation; [0015]FIG. 7 is a view showing another first chip model for power supply voltage fluctuation; [0016]FIG. 8 is a view showing another first chip model for ground voltage fluctuation; [0017]FIG. 9 is a view showing another second chip model for power supply voltage fluctuation; [0018]FIG. 10 is a view showing another second chip model for ground voltage fluctuation; [0019]FIG. 11 is a flowchart showing a design method in accordance with the first embodiment; [0020]FIG. 12 is a view for use in describing how to decide impedances of the first and the second chip models; [0021]FIG. 13 is another view for use in describing how to decide impedances of the first and the second chip models; Continue reading about Method for designing semiconductor package, system for aiding to design semiconductor package, and computer program product therefor... Full patent description for Method for designing semiconductor package, system for aiding to design semiconductor package, and computer program product therefor Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Method for designing semiconductor package, system for aiding to design semiconductor package, and computer program product therefor patent application. Patent Applications in related categories: 20090282381 - Electronic design automation tool and method for optimizing the placement of process monitors in an integrated circuit - An electronic design automation (EDA) tool for and method of optimizing a placement of process monitors (PMs) in an integrated circuit (IC). In one embodiment, the EDA tool includes: (1) a critical path/cell identifier configured to identify critical paths and critical cells in the IC, (2) a candidate PM position ... 20090282381 - Electronic design automation tool and method for optimizing the placement of process monitors in an integrated circuit - An electronic design automation (EDA) tool for and method of optimizing a placement of process monitors (PMs) in an integrated circuit (IC). In one embodiment, the EDA tool includes: (1) a critical path/cell identifier configured to identify critical paths and critical cells in the IC, (2) a candidate PM position ... ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. Start now! - Receive info on patent apps like Method for designing semiconductor package, system for aiding to design semiconductor package, and computer program product therefor or other areas of interest. ### Previous Patent Application: Delay analyzing method, delay analyzing apparatus, and computer product Next Patent Application: Routing display facilitating task of removing error Industry Class: Data processing: design and analysis of circuit or semiconductor mask ### FreshPatents.com Support Thank you for viewing the Method for designing semiconductor package, system for aiding to design semiconductor package, and computer program product therefor patent info. IP-related news and info Results in 0.14568 seconds Other interesting Feshpatents.com categories: Qualcomm , Schering-Plough , Schlumberger , Seagate , Siemens , Texas Instruments , 174 |
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