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  Method for changing physical layout data using virtual layerUSPTO Application #: 20080046849Title: Method for changing physical layout data using virtual layer Abstract: A method for changing physical layout data using a virtual layer is provided. The method codes a target design and synthesizes a logic for it. It may generate a virtual layer, places logic blocks at positions and route them for connection to execution elements. Wiring resistance or capacitance values may be extracted. A timing check may be performed and crosstalk may be analyzed for physical implementation. Interconnections and wirings of transistors may be checked for correspondence with the circuit. Wiring spaces and gate lengths may be checked for compliance with preset specifications. A mask based on the virtual layer may be produced. Thus, the virtual layer is generated by software prior to physical verification when physical layout data is changed, which allows use of LVS/DRC suitable for a fab in which actual processes are performed, achieving reliable physical verification. (end of abstract) Agent: Sherr & Nourse, PLLC - Herndon, VA, US Inventor: Seung-Ho Choi USPTO Applicaton #: 20080046849 - Class: 716 6 (USPTO) The Patent Description & Claims data below is from USPTO Patent Application 20080046849. Brief Patent Description - Full Patent Description - Patent Application Claims
[0001]The present application claims priority under 35 U.S.C. 119 to Korean Patent Application No. 10-2006-0077193, filed on Aug. 16, 2006, which is hereby incorporated by reference in its entirety. BACKGROUND [0002]To efficiently use fab resources and to increase productivity, physical layout data (for example, physical library or GDSII data) from a specific fab may be made available to a different fab to allow both fabs to produce the same products. This not only increases productivity but also increases the efficiency of utilization of existing fab resources. [0003]A layer map file is used when physical layout data is transferred. If new layers are required in a fab into which the physical layout data is transferred, the layers must be generated. For example, an artisan library introduced in fab A for 0.18 nm processes is transferred to an existing fab B for 0.18nm processes, so that products can be manufactured in both fabs, thereby increasing the efficiency of use of the fab resources. If fab B uses two layers including an N active layer and a P active layer, and fab A uses one common active layer, new layers (e.g. an N active layer and a P active layer) must be generated if there are N and P implant layers surrounding a common active layer. [0004]A method for transferring physical layout data uses a Manufacturing Electronic Beam Exposure System (MEBES) to generate such new layers (e.g. N and P active layers) when creating mask data and allows physical layout data to be transferred from fab A to fab B. [0005]However, a method may not generate new layers suitable for fab B since, in the design flow, a Logic Versus Schematic/Design Rule Check (LVS/DRC) is performed before mask data is created. Therefore, even though the fab B is used, physical verification may be performed using the LVS/DRC for fab A, thereby causing heterogeneity between the LVS/DRCs for the two fabs. Thus, when physical layout data is verified, the reliability of the verification may not be ensured. SUMMARY [0006]Embodiments relate to a method for changing physical layout data using a virtual layer, wherein a virtual layer is generated by software prior to physical verification when physical layout data is changed, which makes it possible to use a Logic Versus Schematic/Design Rule Check (LVS/DRC) suitable for a fab (which is short for a fabrication or a fabrication facility) in which actual processes are to be carried out, thereby achieving reliable physical verification. [0007]Embodiments relate to a method for changing physical layout data using a virtual layer, which may maximize reliability of verification of a physical layout. Embodiments relate to a method for changing physical layout data using a virtual layer, wherein a virtual layer is generated by software prior to physical verification when physical layout data is changed, which makes it possible to use a Logic Versus Schematic/Design Rule Check (LVS/DRC) suitable for a fab in which actual processes are to be carried out, thereby achieving reliable physical verification. [0008]Embodiments relate to a method for changing physical layout data using a virtual layer which may include at least one of the following steps: Coding a target design and synthesizing logic for the coded target design. Generating a virtual layer. Placing logic blocks at corresponding positions and routing the logic blocks for connection to execution elements. Extracting wiring resistance or capacitance values and performing a timing check and a crosstalk analysis for physical implementation. Checking whether interconnections and wirings of transistors match a predetermined circuit and checking whether wiring spaces and gate lengths comply with preset specifications. Producing a mask based on the virtual layer. [0009]In embodiments, a method for changing physical layout data using a virtual layer in standard logic cells may include at least one of the following steps: Determining whether N and P active layer names are present. If N and P active layer names are present, determining whether a top cell has a hierarchy. If the top cell has a hierarchy, creating a lower cell list. Generating an N active virtual layer and a P active virtual layer in a lower cell. Deleting an existing common active layer from the lower cell. Determining whether a current cell is a last in the lower cell list. If the current cell is the last in the lower cell list, generating an N active virtual layer and a P active virtual layer in the top cell. Deleting an existing common active layer from the top cell. [0010]In embodiments, a method for changing physical layout data using a virtual layer in I/O pad cells may include at least one of the following steps: Determining whether N and P active layer names are present. If N and P active layer names are present, determining whether a top cell has a hierarchy. If the top cell has a hierarchy, temporarily flattening lower cells of the top cell. Generating an N active virtual layer and a P active virtual layer in the flattened top cell. Deleting an existing common active layer from the flattened top cell and generating a new instance cell. Canceling the temporary flattening of the top cell. Instantiating the instance cell in the top cell. DRAWINGS [0011]Example FIGS. 1A and 1B illustrate an original layout before it is changed using a Cadence SKILL program according to embodiments and a layout after it is changed using the Cadence SKILL program, respectively. [0012]Example FIGS. 2A and 2B illustrate problems that may occur when an algorithm for standard logic is applied to I/O pad cells. [0013]Example FIG. 3 is a flow chart illustrating a procedure for changing physical layout data using a virtual layer, according to embodiments. [0014]Example FIG. 4 is a flow chart illustrating a method for changing physical layout data using a virtual layer in standard logic cells, according to embodiments. [0015]Example FIG. 5 is a flow chart illustrating a method for changing physical layout data using a virtual layer in I/O pad cells, according to embodiments. DESCRIPTION [0016]Example Table 1 shows part of a Cadence SKILL program for standard logic to implement a virtual layer according to embodiments. TABLE-US-00001 TABLE 1 (defun pghCreateActLayersCell (lib cell oldActLayer nimpLayer pimpLayer newNactLayer newPactLayer) (letStar ((cv (dbOpenCellViewByType lib cell "layout" "maskLayout" "a")) (shapeList cv~>shapes) ;Check existence of layer name ; (if !(existLayer? oldActLayer cv) then ; (pghDialogBox "Active layer name does not exist, Please check again!") ; else (if !(existLayer? newNactLayer cv) then ; (pghDialogBox "N+ Active layer name does not exist, Please check again!") ; else (if !(existLayer? newPactLayer cv) then ; (pghDialogBox "P+ Active layer name does not exist, Please check again!") ; ) ; ) ; ) ; Create new n-active Layer (if (cv~>shapes != nil) then [0017]The Cadence SKILL program may be implemented in two types, one for standard logic and the other for Input/Output (I/O) pads. Example processing methods will be described in detail with reference to FIG. 3. [0018]As shown in example FIGS. 1A and 1B, the original layout includes a common active layer 100, a P implant layer 110, and an N implant layer 120. The Cadence SKILL program, or other high-level interactive programming language, may be used to AND the common active layer 100 and the P implant layer 110 to generate a P active layer 112 shown in example FIG. IB. The Cadence SKILL program, or other high-level interactive programming language, may also be used to AND the common active layer 100 and the N implant layer 120 to generate an N active layer 122 shown in example FIG. 1B. Common active layer 100 is then deleted. [0019]This algorithm may be appropriate for standard logic cells since their hierarchy is simple and their common active layers are present in one level. When this algorithm is performed for I/O pad cells, a number of Design Rule Check (DRC) errors may occur in active layers since their hierarchy is more complex than that of the standard logic cells. A common active layer, an N implant layer, and a P implant layer may be drawn in different levels. Details of these problems will be described below with reference to example FIGS. 2A and 2B. Continue reading... Full patent description for Method for changing physical layout data using virtual layer Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Method for changing physical layout data using virtual layer patent application. Patent Applications in related categories: 20080172643 - High-speed leaf clock frequency-divider/splitter - A novel clock splitter that has a local internal clock frequency-divider is presented. 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