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  Method and system of informing a micro-sequence of operand widthUSPTO Application #: 20060026392Title: Method and system of informing a micro-sequence of operand width Abstract: A method and system of informing a micro-sequence of operand width. At least some of the illustrative embodiments may be a method comprising fetching a first opcode, asserting a flag if the first opcode modifies an operand width of a subsequent opcode, fetching a second opcode, triggering a micro-sequence based on the opcode, reading the flag by instructions of the micro-sequence, and fetching an operand of the second opcode by the micro-sequence (the bit width of the operand based on a state of the flag). (end of abstract) Agent: Texas Instruments Incorporated - Dallas, TX, US Inventors: Gilbert Cabillic, Jean-Philippe Lesot, Gerard Chauvel USPTO Applicaton #: 20060026392 - Class: 712210000 (USPTO) Related Patent Categories: Electrical Computers And Digital Processing Systems: Processing Architectures And Instruction Processing (e.g., Processors), Instruction Decoding (e.g., By Microinstruction, Start Address Generator, Hardwired), Decoding Instruction To Accommodate Variable Length Instruction Or Operand The Patent Description & Claims data below is from USPTO Patent Application 20060026392. Brief Patent Description - Full Patent Description - Patent Application Claims
CROSS-REFERENCE TO RELATED APPLICATIONS [0001] This application claims the benefit of European Patent Application No. 04291918.3, filed Jul. 27, 2004, incorporated by reference herein as if reproduced in full below. BACKGROUND OF THE INVENTION [0002] 1. Technical Field of the Invention [0003] The present invention relates to processors and more particularly to the use of micro-sequences in the efficient execution of code (e.g., Java.TM. bytecodes). [0004] 2. Background Information [0005] Some processors have the ability to execute Java.TM. bytecodes directly (an "opcode" being a single member of the group bytecodes), or the functionality desired may be performed by way of "micro-sequences." A stacked-based opcode may be used when a stack-based implementation works better for the desired function, and register-based mirco-sequence may be used when a register-based implementation works better for the desired function. Co-pending and commonly assigned published application US2004/0024999 describes processors having the ability to execute an opcode, or have the opcode trigger a micro-sequence. [0006] Whether a desired function is implemented directly by an opcode, or by a micro-sequence, the width of an operand (the operand pointing to local variables, with each local variable 32 bits in width) is indicated by the presence or absence of another opcode known as "WIDE." In particular, when an opcode is immediately preceded by a WIDE opcode, the operand width is greater than if the WIDE opcode is not present. For example, a directly executed Java.TM. opcode "ILOAD" (integer load), when not preceded by WIDE, may fetch a 32 bit local variable from the location indicated by an eight bit operand. When ILOAD is immediately preceded by a WIDE opcode, the ILOAD opcode may fetch a 32 bit local variable from the location indicated by an sixteen bit operand. Thus, WIDE extends the number of available local variables to 65,536, though each local variable is still 32 bits in width regardless of the presence or absence of WIDE. When executing opcodes directly, the processor decodes the WIDE and adjusts fetched operand width accordingly. However, if the opcode triggers a micro-sequence, fetching of the operand is performed by register-based micro-sequences that are unaware of whether the opcode that triggered the micro-sequence was preceded by a WIDE opcode. [0007] In order for a micro-sequence to determine the operand width, the micro-sequence may have to analyze the opcode instruction stream by reading the instruction stream through data cache reads. Inasmuch as the opcode instruction stream may be present in the processor's instruction cache and not the data cache, the initial attempt to read the instruction stream through the data cache results in a cache miss. Thus, significant processor time is expended by a micro-sequence reading the various triggering opcodes and determining the operand width. SUMMARY [0008] The problems noted above are solved in large part by a method and system of informing a micro-sequence of operand width. At least some of the illustrative embodiments may be a method comprising fetching a first opcode, asserting a flag if the first opcode modifies an operand width of a subsequent opcode, fetching a second opcode, triggering a micro-sequence based on the opcode, reading the flag by instructions of the micro-sequence, and fetching an operand of the second opcode by the micro-sequence (the bit width of the operand based on a state of the flag). NOTATION AND NOMENCLATURE [0009] Certain terms are used throughout the following description and claims to refer to particular system components. As one skilled in the art will appreciate, semiconductor companies may refer to a component by different names. This document does not intend to distinguish between components that differ in name but not function. In the following discussion and in the claims, the terms "including" and "comprising" are used in an open-ended fashion, and thus should be interpreted to mean "including, but not limited to . . .". Also, the term "couple" or "couples" is intended to mean either an indirect or direct connection. Thus, if a first device couples to a second device, that connection may be through a direct connection, or through an indirect connection via other devices and connections. BRIEF DESCRIPTION OF THE DRAWINGS [0010] For a more detailed description of the preferred embodiments of the present invention, reference will now be made to the accompanying drawings, wherein: [0011] FIG. 1 shows a diagram of a system in accordance with embodiments of the invention; [0012] FIG. 2 shows a block diagram of the JSM of FIG. 1 in accordance with embodiments of the invention; [0013] FIG. 3 shows various registers used in the JSM of FIGS. 1 and 2; [0014] FIG. 4 illustrates operation of the JSM to trigger "micro-sequences"; [0015] FIG. 5 illustrates a method in accordance with embodiments of the invention; and [0016] FIG. 6 depicts an illustrative embodiment of the system described herein. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS [0017] The following discussion is directed to various embodiments of the invention. Although one or more of these embodiments may be preferred, the embodiments disclosed should not be interpreted, or otherwise used, as limiting the scope of the disclosure, unless otherwise specified. In addition, one skilled in the art will understand that the following description has broad application, and the discussion of any embodiments is meant only to be exemplary of those embodiments, and not intended to intimate that the scope of the disclosure, is limited to those embodiments. [0018] The subject matter disclosed herein is directed to a programmable electronic device such as a processor. The processor described herein is particularly suited for executing Java.TM. bytecodes, or comparable code. Java.TM. itself is particularly suited for embedded applications as it is a relatively "dense" language, meaning that on average each instruction may perform a large number of functions compared to other programming languages. The dense nature of Java.TM. is of particular benefit for portable, battery-operated devices with small amounts of memory. The reason, however, for executing Java.TM. code is not material to this disclosure or the claims which follow. Further, the processor advantageously has one or more features that permit the execution of the Java.TM. code to be accelerated. Continue reading... Full patent description for Method and system of informing a micro-sequence of operand width Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Method and system of informing a micro-sequence of operand width patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. 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