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Method and system for transmission and reception of asynchronously multiplexed signalsRelated Patent Categories: Multiplex Communications, Pathfinding Or Routing, Switching A Message Which Includes An Address Header, Message Transmitted Using Fixed Length Packets (e.g., Atm Cells), Multiprotocol NetworkMethod and system for transmission and reception of asynchronously multiplexed signals description/claimsThe Patent Description & Claims data below is from USPTO Patent Application 20060193325, Method and system for transmission and reception of asynchronously multiplexed signals. Brief Patent Description - Full Patent Description - Patent Application Claims
BACKGROUND OF THE INVENTION [0001] 1. Field of the Invention [0002] The present invention relates generally to communications systems and more specifically to a method and system for transmission and reception of asynchronously (statistically) multiplexed signals onto a common transmission medium. The present invention is particularly useful for asynchronously multiplexing data units of different format such as ATM cells and frames (i.e., layer-2 frames) in which IP (Internet Protocol) packets are encapsulated. [0003] 2. Description of the Related Art [0004] Demand for high speed communication systems is increasing to meet multimedia communications services (audio, video and the Internet). Physical interfaces for implementing high speed communications have been deployed to provide a wide range of different services corresponding to networks of different architecture. For multimedia communications, ATM (asynchronous transfer mode) cells are the most promising data format for transporting user traffic as a multimedia platform. In addition, high-speed transport interfaces are increasingly used for interfacing high-capacity routers. However, there is an increasing amount of processing burden on the transport interfaces for assembling data traffic into ATM cells and disassembling ATM cells to original format. The transport interfaces thus represent a bottleneck for high speed transmission. One solution to this problem is the use of point-to-point protocol (PPP) frames in the transport interface. However, a need will arise to multiplex PPP frames with ATM cells over a transmission system such as SONET (synchronous optical network. Because of their difference in data format, PPP frames and ATM cells must be segmented into bytes and alternately multiplexed onto synchronized time slots. However, it is impossible to control the allocated bandwidths according to traffic needs. Alternatively, WDM (wavelength division multiplexing) technique may be used to carry PPP frames and ATM cells on different wavelengths to be multiplexed onto a common optical link. However, efficient resource utilization cannot be achieved because of the inability to control the allocated bandwidth according to varying traffic. In addition, the use of two wavelengths represents a waste of one wavelength which could be otherwise used for other high speed traffic. [0005] In addition, a need may exist for asynchronously multiplexing data units of same format but different lengths. SUMMARY OF THE INVENTION [0006] It is therefore an object of the present invention to provide a method and system for asynchronously multiplexing data units regardless of their original data structure and their data length. [0007] The object of the present invention is obtained by forming data units so that the header of each of the data units contains an equal number of physical header bits and an header error check code resulting from division of the physical header bits by an identical generator polynomial and then summing to the header error check code a remainder of division of hypothetical header bits by the generator polynomial, the hypothetical header bits being greater in number than the physical header bits. [0008] According to one aspect of the present invention, there is provided a communication method comprising the steps of receiving a first data unit containing first header bits of a first payload signal and a first error check code representing a remainder of division of the first header bits by a generator polynomial, the first header bits being equal in number to second header bits of a second payload signal of a second data unit, the generator polynomial being used to divide the second header bits to produce a second error check code, and summing a remainder of division of hypothetical header bits by the generator polynomial to the first error check code, the hypothetical header bits being greater in number than the first header bits, whereby the first and second data units can be distinguished from each other by different error check results of the first and second data units. [0009] The hypothetical header bits are composed of higher significant bits of non-zero value and all-zero lower significant bits, the lower significant bits being equal in number to the first header bits plus the error check code. Further, the hypothetical header bits may correspond in number to the maximum degree of an irreducible polynomial. [0010] At a transmit site, the first and second data units are asynchronously multiplexed onto a common medium and transmitted to a receive site. At the receive site, an error check is performed on the header bits of the multiplexed signal by using the same generator polynomial as that used in the transmit site to produce a first result. A second result is produced by summing to the first result the same second remainder as that produced at the transmit site. Depending on the first and second results, a decision is made as to whether the received signal corresponds to the first data unit or the second data unit. [0011] The receive site identifies the received signal as a first data unit when it detects the presence of a one-bit error in the first result and no bit error in the second result and identifies the received signal as a second data unit when it detects the presence of a one-bit error in the second result and no bit error in the first result. Further, the receive site identifies the received signal as a first data unit when it detects the presence of a two-bit error in the first result and a one-bit error in the second result and identifies the received signal as a second data unit when it detects the presence of a two-bit error in the second result and a one-bit error in the first result. [0012] In a practical aspect, the first data unit is a layer-2 frame in which layer-3 packets are encapsulated and the second data unit is an ATM cell. The generator polynomial is x.sup.8+x.sup.2+x+1 which is used to divide the hypothetical header bits which may extend up to 127 bits. Specifically, the hypothetical header bits are composed of all-zero lower-significant bits which are in the range from the 0-th to the 39-th bit position corresponding to the first header bits, and higher-significant bits of non-zero value which are in the range from the 40-th to the 126-th bit position. A constant value (=x.sup.7+x.sup.5+x.sup.3+1) is added to the first error check code of the layer-2 frame as well as to the second error check code of the ATM cell. At the receive site, an error check is performed on the header bits of a multiplexed data unit by using the generator polynomial x.sup.8+x.sup.2+x+1 to produce a result. A sum of the constant value and the second remainder as those used at the transmit site is added to the result to produce a first added result, and the same second remainder is added to the result to produce a second added result. Depending on the first and second added results, a decision is made as to whether the received signal is a layer-2 frame or an ATM cell. [0013] The amount of information carried by the multiplexed first data unit may be limited when the second data unit is requesting high quality of service and an idle data unit may be transmitted when the first and second data units are not present on the common medium. The second data units may be transmitted immediately following the start timing of a superframe and the first data units follow when the second data units are requesting high quality of service. [0014] According to another aspect, the present invention provides a communication method comprising the steps of producing, for a first payload signal of a first data unit, first header bits equal in number to second header bits of a second payload signal of a second data unit, dividing the first header bits by a generator polynomial to produce a first error check code, the generator polynomial being equal to a generator polynomial with which the second header bits are divided to produce a second error check code, producing a sum of a remainder of division of hypothetical header bits by the generator polynomial to the first error check code, the hypothetical header bits being greater in number than the second header bits, and forming the first data unit with the second header bits, the sum and the first payload signal, whereby the first and second data units can be distinguished from each other by different error check results of the first and second data units. [0015] According to a further aspect, the present invention provides a communication method which comprises transmitting a first data unit containing first header bits, a first error check code and a first payload signal through a transmission medium, and receiving the first data unit through the transmission medium and producing a sum of a remainder of division of hypothetical header bits by that generator polynomial to the first error check code, the hypothetical header bits being greater in number than the first header bits, and reformulating a first data unit with the first header bits, the sum and the first payload signal, whereby the reformulated first data unit can be distinguished from a second data unit by different error check results of the first and second data units, wherein the second data unit contains second headers equal in number to the first header bits, a second error check code resulting from division of the second header bits by that generator polynomial. [0016] According to a still further aspect, a first data unit is transmitted from a transmit site through a transmission medium, the first data unit containing header bits and a sum of a first error check code resulting from division of the first header bits with a generator polynomial and a remainder resulting from division by that generator polynomial of hypothetical header bits greater in number than the first header bits. The first data unit is received by a receive site, where that remainder is subtracted from the received first data unit, whereby the received first data unit is converted to a data unit which can be distinguished from a data unit which is identical in format to the received first data unit. [0017] According to a still further aspect, the present invention provides a communication circuit comprising a storage circuit including a first field for storing first header bits of a first payload signal of a first data unit, a second field containing a first error check code resulting from division of the first header bits by a generator polynomial, and a third field for storing the first payload signal, the first header bits being equal in number to second header bits of a second payload signal of a second data unit, and the generator polynomial being used to divide the second header bits to produce a second error check code, and an adder circuit for summing a remainder of division of hypothetical header bits by the generator polynomial to the first error check code, the hypothetical header bits being greater in number than a total number of bits in the first and second fields, whereby the first data unit can be distinguished from each other by different error check results of the first and second data units. [0018] According to a still further aspect, the present invention provides a communication circuit comprising a storage circuit including a first field for storing first header bits of a first payload signal of a first data unit, a second field, and a third field for storing the first payload signal, the first header bits being equal in number to second header bits of a second payload signal of a second data unit, and the generator polynomial being used to divide the second header bits to produce a second error check code, division circuitry for dividing the first header bits by the generator polynomial to produce a first error check code, and an adder for summing a remainder of division of hypothetical header bits by the generator polynomial to the first error check code to produce a sum and inserting the sum into the second field of the storage circuit, the hypothetical header bits being greater in number than a total number of bits in the first and second fields, whereby the first and second data units can be distinguished from each other by different error check results of the first and second data units. [0019] According to a still further aspect, the present invention provides a communication circuit comprising a storage circuit including a first field for storing first header bits of a first payload signal of a received first data unit, a second field containing a first error check code which equals a sum of a first remainder resulting from division of the first header bits by a generator polynomial and a second remainder resulting from division of hypothetical header bits by the generator polynomial greater in number than the first header bits, and a third field for storing the first payload signal, the first header bits being equal in number to second header bits of a second payload signal of a second data unit, and the generator polynomial being used to divide the second header bits to produce a second error check code of the second data unit, whereby the first and second data units can be distinguished from each other by different error check results of the first and second data units, and a subtractor circuit for subtracting the second remainder from the first error check code of the received first data unit, whereby the received first data unit is converted to a data unit which can be distinguished from a data unit identical in format to the received first data unit by different error check results. [0020] A storage circuit may be further provided for receiving a data unit containing a payload, header bits and a sum of an error check code resulting from division of the header bits by a generator polynomial and a remainder of division of hypothetical header bits greater in number than the header bits. A subtractor circuit is provided for subtracting the remainder from the sum of the received data unit, whereby the received data unit is converted to a first data unit which can be distinguished from a second data unit identical in format to the received data unit by different error check results of the first and second data units. BRIEF DESCRIPTION OF THE DRAWIGNS [0021] The present invention will be described in detail further with reference to the following drawings, in which: Continue reading about Method and system for transmission and reception of asynchronously multiplexed signals... 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