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Method and system for providing indeterminate read data latency in a memory systemRelated Patent Categories: Multiplex Communications, Data Flow Congestion Prevention Or Control, Flow Control Of Data Transmission Through A NetworkMethod and system for providing indeterminate read data latency in a memory system description/claimsThe Patent Description & Claims data below is from USPTO Patent Application 20070183331, Method and system for providing indeterminate read data latency in a memory system. Brief Patent Description - Full Patent Description - Patent Application Claims
CROSS-REFERENCE TO RELATED APPLICATIONS [0001] This application is a continuation of U.S. patent application Ser. No. 11/289,193 filed Nov. 28, 2005, the contents of which are incorporated by reference herein in their entirety. BACKGROUND OF THE INVENTION [0002] This invention relates to memory systems comprised of hub devices connected to a memory controller by a daisy chained channel. The hub devices are attached to, or reside upon, memory modules that contain memory devices. More particularly, this invention relates to the flow control of read data and the identification of read data returned to the controller by each hub device. [0003] Many high performance computing main memory systems use multiple fully buffered memory modules connected to a memory controller by one or more channels. The memory modules contain a hub device and multiple memory devices. The hub device fully buffers command, address and data signals between the memory controller and the memory devices. The flow of read data is controlled using either a leveled latency or position dependant latency technique. In both cases, the memory controller is able to predict the return time of read data requested from the memory modules and to schedule commands to avoid collisions as read data is merged onto the controller interface by each memory module. [0004] In some cases, the memory controller is able to issue a read data delay adder along with the read command. This instructs the targeted hub device to add additional delay to the return of read data in order to simplify the issuing of commands and to avoid collisions. In all cases, the read data must be returned in the order in which it was requested. Further, the total read data latency must be completely predictable by the memory controller. During run time operations, these two restrictions result in additional gaps being added to packets of read data that are returned from the memory modules. This adds latency to the average read operation. In addition, hubs are not able to use indeterminate techniques to return read data faster or slower than normal. These techniques include, but are not limited to, caching read data locally, reading memory devices speculatively, independently managing memory device address pages, data compression, etc. [0005] To optimize average read data latency under real workload conditions, and to enable advanced hub device capabilities, what is needed is a way to allow memory modules to return read data to the memory controller at an unpredicted time. This must be done in a way that does not corrupt read data and that allows the memory controller to identify each read data packet. Preventing data corruption by avoiding data collisions is especially complicated as hub devices merge local read data onto a cascaded memory controller channel. BRIEF SUMMARY OF THE INVENTION [0006] Exemplary embodiments include a method for providing indeterminate read data latency. The method includes determining if a local data packet has been received. If a local data packet has been received, then the local data packet is stored into a buffer device. The method also includes determining if the buffer device contains a data packet and determining if an upstream driver for transmitting data packets to a memory controller via an upstream channel is idle. If the buffer contains a data packet and the upstream driver is idle, then the data packet is transmitted to the upstream driver. The method further includes determining if an upstream data packet has been received. The upstream data packet is in a frame format that includes a frame start indicator and an identification tag for use by the memory controller in associating the upstream data packet with its corresponding read instruction. If an upstream data packet has been received and the upstream driver is not idle, then the upstream data packet is stored into the buffer device. If an upstream data packet has been received and the buffer device does not contain a data packet and the upstream driver is idle, then the upstream data packet is transmitted to the upstream driver. If the upstream driver is not idle, then any data packets in progress are continued being transmitted to the upstream driver. [0007] Exemplary embodiments include a hub device in a memory system. The hub device includes a device for receiving data packets, an upstream driver for transmitting data packets to a memory controller via an upstream channel and a mechanism including instructions for facilitating indeterminate read data latency. The device for receiving data packets includes an upstream receiver for receiving upstream data packets from a downstream hub device and a memory interface for receiving local data packets from a local storage device. Each data packet is in a frame format that includes a frame start indicator and an identification tag for use by a memory controller in associating the data packet with its corresponding read instruction. The instructions on the mechanism facilitate determining if a local data packet has been received. If a local data packet has been received, then the local data packet is stored into a buffer device. The instructions also facilitate determining if the buffer device contains a data packet and determining if the upstream driver is idle. If the buffer contains a data packet and the upstream driver is idle, then the data packet is transmitted to the upstream driver. The instructions further facilitate determining if an upstream data packet has been received. If an upstream data packet has been received and the upstream driver is not idle, then the upstream data packet is stored into the buffer device. If an upstream data packet has been received and the buffer device does not contain a data packet and the upstream driver is idle, then the upstream data packet is transmitted to the upstream driver. If the upstream driver is not idle, then any data packets in progress are continued being transmitted to the upstream driver. [0008] Exemplary embodiments include a memory subsystem with one or more memory modules. The memory modules include one or more memory devices connected to a memory controller by a daisy chained channel. The read data is returned to the memory controller using a frame format that includes an identification tag and frame start indicator. The memory system also includes one or more hub devices on the memory modules for buffering address, commands and data. The hub devices include controller channel buffers that are used in conjunction with a preemptive local data merge algorithm to minimize read data latency and enable indeterminate read data return times to the memory controller. [0009] Further exemplary embodiments include a memory system with one or more memory modules. The memory modules include memory devices that are connected to a memory controller by a daisy chained channel. The read data is returned to the memory controller using a frame format that includes an identification tag and frame start indicator. The memory system also includes one or more hub devices connected to the memory modules for buffering address, commands and data. The hub devices include controller channel buffers that are used in conjunction with a preemptive local data merge algorithm to minimize read data latency and enable indeterminate read data return times to the memory controller. BRIEF DESCRIPTION OF THE DRAWINGS [0010] Referring now to the drawings wherein like elements are numbered alike in the several FIGURES: [0011] FIG. 1 depicts an exemplary memory system with multiple levels of daisy chained memory modules with point-to-point connections; [0012] FIG. 2 depicts an exemplary memory system with hub devices that are connected to a memory modules and to a memory controller by a daisy chained channel; [0013] FIG. 3 depicts a hub logic device that may be utilized by exemplary embodiments; [0014] FIG. 4 is a exemplary process flow implemented by the hub logic device in exemplary embodiments; and [0015] FIG. 5 is a read data format that may be utilized by exemplary embodiments. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS [0016] Exemplary embodiments utilize controller channel buffers (CCBs), read data frame formats with identification tags and a preemptive data merge technique to enable minimized and indeterminate read data latency. Exemplary embodiments allow memory modules to return read data to a memory controller at an unpredicted time. Identification tag information is added to the read data packet to indicate the read command that the data is a result of, as well as the hub where the data was read. The identification tag information is utilized by the controller to match the read data packet to the read commands issued by the controller. By using the identification tag information, read data can be returned in an order that is different from the issue order of the corresponding read commands. [0017] Exemplary embodiments also provide a preemptive data merge process to prevent data collisions on the upstream channel when implementing the indeterminate read data latency. A CCB is added to the hub device to temporarily store read data. When a memory device on the memory module reads data, the data is transferred from the memory interface to the buffer. When the hub device detects that an upstream data packet (i.e., a data packet being sent to the controller from a hub device that is downstream from the detecting hub device) is not in the middle of being transferred into the detecting hub device via an upstream channel (it typically takes several transfers to send the entire data packet), the detecting hub device checks to see if there is a read data packet in its CCB that is waiting to be sent upstream. If the hub device detects a read data packet in the CCB it drives the read data packet from the CCB onto the upstream data bus. In the meantime, if a new upstream data packet is received via the upstream data bus, the data packet is stored in the CCB on the hub device. In this manner, data packets coming upstream do not collide with data packets being sent upstream from the CCB on the hub device. In the case where there is more than one data packet in the CCB, a variety of methods may be implemented to determine which data packet to send next (e.g., the data packet from the oldest read command may be sent first). [0018] Exemplary embodiments apply to memory systems constructed of one or more memory modules 110 that are connected to a memory controller 102 by a daisy chained memory channel 114 as depicted in FIG. 1. The memory modules 110 contain both a hub device 112 that buffers commands, address and data signals to and from the controller memory channel 114 as well as one or more memory devices 108 connected to the hub device 112. The downstream portion of the memory channel 114, the downstream channel 104, transmits write data and memory operation commands to the hub devices 112. The upstream portion of the controller channel 114, the upstream channel 106, returns requested read data (referred to herein as upstream data packets). [0019] FIG. 2 depicts an alternate exemplary embodiment that includes a memory system constructed of one or more memory modules 110 connected to hub devices 112 that are further connected to a memory controller 102 by a daisy chained memory channel 114. In this embodiment, the hub device 112 is not located on the memory module 110; instead the hub device 112 is in communication with the memory module 110. As depicted in FIG. 2, the memory modules 110 may be in communication with the hub devices 112 via multi-drop connections and/or point-to-point connections. Other hardware configurations are possible, for example exemplary embodiments may utilize only a single level of daisy chained hub devices 112 and/or memory modules 110. Continue reading about Method and system for providing indeterminate read data latency in a memory system... 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