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Method and system for logic verification using mirror interfaceRelated Patent Categories: Data Processing: Design And Analysis Of Circuit Or Semiconductor Mask, Circuit Design, Testing Or Evaluating, Design Verification (e.g., Wiring Line Capacitance, Fan-out Checking, Minimum Path Width)Method and system for logic verification using mirror interface description/claimsThe Patent Description & Claims data below is from USPTO Patent Application 20070204246, Method and system for logic verification using mirror interface. Brief Patent Description - Full Patent Description - Patent Application Claims
CROSS REFERENCE TO RELATED APPLICATIONS [0001] This application is a continuation of U.S. application Ser. No. 10/986,773, filed on Nov. 15, 2004. Application Ser. No. 10/986,773 is a continuation of U.S. application Ser. No. 09/826,035, filed Apr. 4, 2001, now issued as U.S. Pat. No. 6,865,502. The listed applications are assigned to International Business Machines Corporation and the entire contents of each of these applications are incorporated herein by reference. BACKGROUND [0002] The present invention relates generally to the verification of integrated circuit (IC) logic, and more particularly to a method and system for increasing the efficiency and re-usability of verification software. [0003] Before ICs are released to market, the logic designs incorporated therein are typically subject to a testing and de-bugging process known as "verification." Verification of logic designs using simulation software allows a significant number of design flaws to be detected and corrected before incurring the time and expense needed to physically fabricate designs. [0004] Software verification typically entails the use of software "models" of design logic. Such models may be implemented as a set of instructions in a hardware description language (HDL) such as Verilog.RTM.. or VHDL.RTM.. The models execute in a simulation environment and can be programmed to simulate a corresponding hardware implementation. The simulation environment comprises specialized software for interpreting model code and simulating the corresponding hardware device or devices. By applying test stimuli (typically in batches known as "test cases") to a model in simulation, observing the responses of the model and comparing them to expected results, design flaws can be detected and corrected. [0005] Advances in technology have permitted logic designs to be packed with increased density into smaller areas of silicon as compared with past IC devices. This has led to "system-on-a-chip" (SOC) designs. The term "SOC" as used herein refers to combinations of discrete logic blocks, often referred to as "cores," each performing a different function or group of functions. A SOC integrates a plurality of cores into a single silicon device, thereby providing a wide range of functions in a highly compact form. Typically, a SOC comprises its own processor core (often referred to as an "embedded" processor), and will further comprise one or more cores for performing a range of functions often analogous to those of devices in larger-scale systems. [0006] In its developmental stages a core is typically embodied as a simulatable HDL model written at some level of abstraction, or in a mixture of abstraction levels. Levels of abstraction that are generally recognized include a behavioral level, a structural level, and a logic gate level. A core may be in the form of a netlist including behavioral, structural and logic gate elements. [0007] Verification of a SOC presents challenges because of the number of cores and the complexity of interactions involved, both between the cores internally to the SOC, and between the SOC and external logic. An acceptable level of verification demands that a great number of test cases be applied, both to individual components of the SOC, and to the cores interconnected as a system and interfacing with logic external to the SOC. There is a commensurate demand on computer resources and time. Accordingly, techniques which increase the efficiency of verification are at a premium. [0008] According to one standard technique, already-verified models are used to test other models. The electronic design automation (EDA) industry has reached a level of sophistication wherein vendors offer standardized models for use in verification of other models still in development. In particular, such models are typically used for testing cores in a SOC that have external interfaces (i.e., communicate with logic external to the SOC). Such standardized models save the purchaser development resources, are typically well-tested and reliable, and are designed to have a wide range of applicability. [0009] However, there are disadvantages associated with using standardized models. For instance, they can be very costly. Moreover, they can be very complex and provide much more functionality than is needed by the purchaser if only a subset of functions are required. Further, the standardized models must be integrated into existing verification systems, incurring more cost in terms of time and effort. [0010] Alternatively to purchasing and using standardized models, designers may, of course, develop their own testing models. However, this is costly in terms of development time, with the typical result that such models are designed for limited application. Accordingly, they typically have limited functionality and re-usability. [0011] An approach is needed to address the concerns noted in the foregoing. SUMMARY [0012] The present invention overcomes shortcomings of existing art by providing an efficient and economical method and system for testing external interfaces of cores in an SOC. According to the invention, a mirror interface is attached to an external interface of a core undergoing verification. The mirror interface is a copy or duplicate of the interface undergoing verification. [0013] In a preferred embodiment, a standardized, programmable control mechanism is utilized to enable a test case executing in the SOC, for purposes of verifying the external interface, to configure the mirror interface as needed for data transfers to and from the external interface. The control mechanism controls data flow, transfer direction, and data checking. [0014] In the foregoing embodiment, the mirror interface is attached to a bus functional model containing a memory model for storing data received from the external SOC interface during testing, and a processor model for emitting CPU bus cycles. A bi-directional communication mechanism is provided to enable communication between the SOC and the control mechanism. [0015] Because the mirror interface is an exact copy of the external interface undergoing verification, all the I/O connections of the interfaces can be used. Moreover, because the control mechanism is standardized, the invention is highly re-usable. Further, the control mechanism is programmable to be readily adaptable to different interfaces. BRIEF DESCRIPTION OF THE DRAWINGS [0016] FIG. 1A shows a verification test bench according to the present invention; [0017] FIG. 1B shows execution domains of a test case and the control mechanism according to the invention; [0018] FIG. 2 shows connections and signals exchanged between a SOC and a bus functional model and mirror interface via a bidirectional general purpose I/O device; [0019] FIG. 3 shows a process flow of control code for handling data flow, transfer direction, and data checking; and [0020] FIG. 4 shows a general purpose computer system for implementing the invention. Continue reading about Method and system for logic verification using mirror interface... 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