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Method and system for hermetically sealing packages for opticsRelated Patent Categories: Semiconductor Device Manufacturing: Process, Making Device Or Circuit Responsive To Nonelectrical Signal, Physical Stress ResponsiveMethod and system for hermetically sealing packages for optics description/claimsThe Patent Description & Claims data below is from USPTO Patent Application 20070072328, Method and system for hermetically sealing packages for optics. Brief Patent Description - Full Patent Description - Patent Application Claims
CROSS-REFERENCES TO RELATED APPLICATIONS [0001] This application is a continuation of U.S. patent application Ser. No. 10/693,323, filed Oct. 24, 2003, the disclosure of which is incorporated herein by reference in its entirety for all purposes. BACKGROUND OF THE INVENTION [0002] This present invention relates generally to manufacturing objects. More particularly, the invention provides a method and structure for hermetically bonding a transparent cover to a semiconductor substrate. Merely by way of example, the invention has been applied to a transparent glass cover hermetically bonded to a semiconductor wafer containing a micro-mechanical electrical system. The method and structure can be applied to display technology as well as, for example, charge coupled display camera arrays, and infrared arrays. [0003] The packaging of silicon integrated circuits has reached a high level of maturity. FIG. 1 illustrates a simplified diagram of a conventional silicon integrated circuit package. The silicon integrated circuit die 110 is mounted on a submount 115 featuring a ball grid array 120. Wire bonds 125 are attached to the silicon die 110 to provide electrical connection to the submount 115. Typically, the silicon die 110 and the wire bonds 125 are encapsulated using a plastic encapsulant 130. The resulting package is robust and inexpensive. [0004] The package illustrated in FIG. 1 presents several drawbacks in applications that often require more than electrical operation of the silicon integrated circuit. An example of such an application is optical reflection off an array of micro-mirrors or other MEMS structure. For example, these applications typically require the ability to illuminate the top of the silicon integrated circuit with optical energy and subsequently reflect the optical energy off the top of the silicon integrated circuit with high efficiency. The optical properties of the plastic encapsulant, including lack of transparency, non-uniformity of the index of refraction, and surface roughness make these packages unsuitable for this application. Additionally, many MEMS often require an open space above the surface of the silicon integrated circuit to enable the micro-electro-mechanical structures to move in the direction parallel to the plane of the MEMS as well as in the direction perpendicular to the plane of the MEMS. The physical contact that the plastic encapsulant makes with the surface of the integrated circuit, therefore, make this package unsuitable for many MEMS applications. SUMMARY OF THE INVENTION [0005] This present invention relates generally to manufacturing objects. More particularly, the invention provides a method and structure for hermetically bonding a transparent cover to a semiconductor substrate. Merely by way of example, the invention has been applied to a transparent glass cover hermetically bonded to a semiconductor wafer containing a micro-mechanical electrical system. The method and structure can be applied to display technology as well as, for example, charge coupled display camera arrays, and infrared arrays. [0006] In a specific embodiment according to the present invention, a method for hermetically sealing devices is provided. The method includes providing a substrate that includes a plurality of individual chips, each of the chips including a plurality of devices. In this specific embodiment according to the present invention, the chips are arranged in a spatial manner as a first array. The array configuration in this embodiment includes a plurality of first street regions arranged in strips and a plurality of second street regions arranged in strips. The second street regions intersect the first street regions to form the array configuration. The method also includes providing a transparent member of a predetermined thickness. The transparent member in this embodiment includes a plurality of recessed regions within the predetermined thickness and arranged in a spatial manner as a second array. Preferably, each of the recessed regions is bordered by a standoff region. In this specific embodiment, the standoff region has a thickness defined by a portion of the predetermined thickness. The method also includes aligning the transparent member in a manner to couple each of the plurality of recessed regions to a respective one of said plurality of chips. The transparent member is aligned such that the standoff region is coupled to each of the plurality of first street regions and is coupled to each of the plurality of second street regions to enclose each of the chips within one of the respective recessed regions. The method also includes hermetically sealing each of the chips within one of the respective recessed regions by contacting the standoff region of the transparent member to the plurality of first street regions and second street regions. Preferably, the hermetic sealing uses at least a bonding process to isolate each of the chips within one of the recessed regions. [0007] In an alternative specific embodiment, the invention provides a system for hermetically sealing devices. The system comprises a substrate configured to include a plurality of individual chips. Each of the chips includes a plurality of devices. Additionally, each of the chips are arranged in a spatial manner as a first array. The array configuration includes a plurality of first street regions arranged in strips and a plurality of second street regions arranged in strips. The second street regions intersect the first street regions to form the array configuration. The system further comprises a transparent member of a predetermined thickness. The transparent member is configured to include a plurality of recessed regions within the predetermined thickness. The plurality of recessed regions are arranged in a spatial manner as a second array. Furthermore, each of the recessed regions are bordered by a standoff region having a thickness defined by a portion of the predetermined thickness. The substrate and the transparent member are aligned in a manner to couple each of the plurality of recessed regions to a respective one of said plurality of chips. Accordingly, the standoff region is coupled to each of the plurality of first street regions and is coupled to each of the plurality of second street regions to enclose each of the chips within one of the respective recessed regions. Each of the chips within one of the respective recessed regions is hermetically sealed by contacting the standoff region of the transparent member to the plurality of first street regions and second street regions using at least a bonding process to isolate each of the chips within one of the recessed regions. [0008] These and other objects and features of the present invention and the manner of obtaining them will become apparent to those skilled in the art, and the invention itself will be best understood by reference to the following detailed description read in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS [0009] FIG. 1 is a simplified diagram of a conventional silicon integrated circuit package. [0010] FIG. 2 is a simplified diagram of a conventional hermetically sealed transparent integrated circuit package. [0011] FIGS. 3A-3D are simplified diagrams of a wafer-level hermetically sealed package according to an embodiment of the present invention. [0012] FIGS. 4A and 4B are simplified diagrams of a transparent member according to an embodiment of the present invention formed from two transparent components. [0013] FIG. 5A is a simplified top view of a transparent member and substrate according to an embodiment of the present invention at the time of hermetic sealing. [0014] FIG. 5B is a simplified diagram of four transparent members and a substrate according to an alternative embodiment of the present invention at the time of hermetic sealing. [0015] FIG. 6 is a simplified diagram of a single micro-mirror chip after hermetic sealing according to an embodiment of the present invention. [0016] FIG. 7 is a simplified diagram of a die level package including a hermetically sealed die according to an embodiment of the present invention. [0017] FIG. 8 is a simplified diagram illustrating the operation of a reflective system according to an embodiment of the present invention. DETAILED DESCRIPTION OF SPECIFIC EMBODIMENTS [0018] According to the present invention, techniques for manufacturing objects are provided. More particularly, the invention provides a method and system for hermetically sealing packages for objects. Merely by way of example, the invention has been applied to the hermetic sealing of an optical micro-mirror package. The method and system can be applied to sensor technology as well as other MEMS devices where hermetic packaging is required. [0019] FIG. 2 illustrates a simplified diagram of a conventional hermetically sealed transparent integrated circuit package useful for optical illumination of a micro-mirror array. In FIG. 2, a silicon MEMS die 210 featuring a micro-mirror array 215 is mounted on a submount 220. The die is attached to the submount using die attach procedures that are compatible with hermetically sealed packaging requirements well known to those skilled in the art. Wire bonds 225 are attached to the silicon die and the submount as with the package illustrated in FIG. 1. Continue reading about Method and system for hermetically sealing packages for optics... Full patent description for Method and system for hermetically sealing packages for optics Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Method and system for hermetically sealing packages for optics patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. 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