| Method and system for filter loop with saturation -> Monitor Keywords |
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  Method and system for filter loop with saturationRelated Patent Categories: Pulse Or Digital Communications, Equalizers, Automatic, AdaptiveThe Patent Description & Claims data below is from USPTO Patent Application 20070019720. Brief Patent Description - Full Patent Description - Patent Application Claims
RELATED APPLICATIONS [0001] [Not Applicable] FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT [0002] [Not Applicable] [MICROFICHE/COPYRIGHT REFERENCE] [0003] [Not Applicable] FIELD OF THE INVENTION [0004] Certain embodiments of the invention relate to processing of signals. More specifically, certain embodiments of the invention relate to a method and system for a filter loop with saturation. BACKGROUND OF THE INVENTION [0005] High-speed digital communication networks over copper and optical fiber are used in many network communication and digital storage applications. Ethernet and Fiber Channel are two widely used communication protocols, which continue to evolve in response to increasing demands for higher bandwidth in digital communication systems. [0006] As the demand for higher data rates and bandwidth continues to increase, equipment vendors are continuously being forced to employ new design techniques for manufacturing network equipment and integrated circuits capable of handling these increased data rates and data processing requirements. For example, timely signal processing of packetized data is central to the operation of Voice over IP (VOIP) telephones and networks. In this regard, digital signal processing systems may be adapted to utilize one or more filter loops prior to transmission and/or after reception of packetized data. A filter loop may be utilized to transform an input signal and generate an output signal within a specific signal range. Conventional filter loops, however, utilize signal conversions in the circuit critical signal path, or the longest signal processing path within the filter loop. Signal format conversions within the circuit's critical path may significantly decrease the processing efficiency of Voice over IP or other digital signal processing systems. [0007] Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such systems with the present invention as set forth in the remainder of the present application with reference to the drawings. BRIEF SUMMARY OF THE INVENTION [0008] A system and/or method for a filter loop with saturation, substantially as shown in and/or described in connection with at least one of the figures, as set forth more completely in the claims. [0009] Various advantages, aspects and novel features of the present invention, as well as details of an illustrated embodiment thereof, will be more fully understood from the following description and drawings. BRIEF DESCRIPTION OF SEVERAL VIEWS OF THE DRAWINGS [0010] FIG. 1 is a block diagram of an exemplary filter loop, which may be utilized in accordance with an embodiment of the invention. [0011] FIG. 2 is a block diagram of an exemplary filter loop with a delayed output, in accordance with an embodiment of the invention. [0012] FIG. 3 is a block diagram of an exemplary filter loop, which may be utilized in accordance with an embodiment of the invention. [0013] FIG. 4 is a flow diagram of exemplary steps for processing signals, in accordance with an embodiment of the invention. [0014] FIG. 5 is an block diagram of an exemplary signal processing system for filtering data, in accordance with an embodiment of the invention. DETAILED DESCRIPTION OF THE INVENTION [0015] Certain aspects of the invention may be found in a method and system for a filter loop with saturation. In one embodiment of the invention, an input signal and a plurality of saturation limit signals may be filtered in a first operating cycle utilizing carry-save arithmetic. Simultaneously, in a second operating cycle, the input signal may be converted to binary form and an output signal may be selected from a plurality of signals calculated in a previous operation cycle. In this regard, by utilizing two simultaneous operating cycles with a single binary conversion, signal conversions within the filter loop's critical path from carry-save to binary format, for example, may be performed in parallel with other operations. Accordingly, this results in increased signal processing efficiency of the filter loop. Furthermore, by utilizing two simultaneous operating cycles rather than a single operating cycle utilized by conventional filter loops, the filter loop signal throughput may be approximately doubled. [0016] FIG. 1 is a block diagram of an exemplary filter loop, which may be utilized in accordance with an embodiment of the invention. Referring to FIG. 1, the filter loop 100 may comprise an adder 104, a selector 106, a multiplexer 108, and a feedback filter 112. The feedback filter 112 may be an infinite impulse response (IIR) filter and may comprise delay blocks 114, . . . , 118 and 120, . . . , 124, adder 138, and multiplier blocks 132, . . . , 136 and 126, . . . , 130. The multiplier blocks 132, . . . , 136 may utilize determined multiplier values b.sub.1, . . . , b.sub.k, and multiplier blocks 126, . . . , 130 may utilize determined multiplier values a.sub.1, . . . , a.sub.n. Even though an IIR filter is illustrated in FIG. 1, the present invention may not be so limited and other types of filters, such as a finite impulse response (FIR) filter may be also utilized for filtering a feedback signal. Continue reading... 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