| Method and system for fabricating and cleaning free-standing nanostructures -> Monitor Keywords |
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  Method and system for fabricating and cleaning free-standing nanostructuresRelated Patent Categories: Semiconductor Device Manufacturing: Process, Making Passive Device (e.g., Resistor, Capacitor, Etc.), Stacked Capacitor, Including Selectively Removing Material To Undercut And Expose Storage Node LayerThe Patent Description & Claims data below is from USPTO Patent Application 20060194404. Brief Patent Description - Full Patent Description - Patent Application Claims
CROSS-REFERENCE TO RELATED APPLICATION [0001] This is a continuation-in-part application of U.S. application Ser. No. 11/066,320, entitled "Method and System for Fabricating Free-Standing Nanostructures" and filed Feb. 25, 2005 which is incorporated herein by reference in its entirety. FIELD OF THE INVENTION [0002] The invention relates to systems and corresponding methods for fabricating and cleaning free-standing nanostructures on a semiconductor wafer. In particular, the invention relates to the field of etching, cleaning, and drying a semiconductor wafer with a patterned layer to fabricate bottom electrode structures on a semiconductor wafer and to cleaning and/or drying the bottom electrode structures. BACKGROUND [0003] One goal in the manufacture of integrated circuits is to continuously decrease feature sizes of the fabricated components. For certain components, like capacitors, shrinking adversely affects the properties of the component. In order to achieve a desired value of capacitance, it is therefore necessary to keep the surface area of the capacitor above a threshold value. This is particularly important for dynamic random access memory cells (DRAM) which call for high integration densities. [0004] As the surface area for a single memory cell decreases, the capacity of the storage capacitor also decreases. For proper operation of the memory cell, a certain minimum capacity (typically on the order of about 30 femto farad) is mandatory for the storage capacitor. If the capacity of the storage capacitor is too small, the charge stored in the storage capacitor is not sufficient to produce a detectable signal. In such a case, the information stored in the memory cell is lost and the memory cell is not operating in a desired manner. [0005] Several methods have been developed to overcome the problems associated with shrinking feature sizes by integrating capacitors of DRAM cells in a three dimensional manner. For example, one method introduces deep trench capacitors which are formed in the substrate of a semiconductor wafer to maintain a large capacitor area with a high capacity while using only a small amount of the surface of the substrate. The selection or access transistor is usually formed on the planar surface of the substrate in this method. [0006] In another example, stacked capacitors are used which are formed on top of a planar surface on the substrate. The selection transistors are formed below the planar surface in this method. The stacked capacitor includes a first electrode and a second electrode with a dielectric layer between the two electrodes. The first electrode (also called bottom electrode) is usually formed as a cylindrical structure on the surface of the substrate by lining trenches of a patterned sacrificial mold layer with the electrode material. Afterwards, the bottom electrodes are released by etching the sacrificial mold layer. Subsequently, the surface of the bottom electrodes are cleaned to be prepared for further processing, including deposition of the dielectric layer and the second or top electrode. [0007] However, with the ever decreasing feature sizes of structures, etching and/or cleaning steps become increasingly difficult. Etching and/or cleaning steps are usually performed by wet processing. Standard wet processing, e.g. rinsing the wafer with ultra pure de-ionized water for cleaning purposes, introduces capillary forces between neighboring structures (e.g., between adjacent bottom electrodes). With reduced feature sizes, this may lead to adhesion of neighboring structures. This is described in Legtenberg et al., "Stiction of surface macromachined structures after rinsing and drying: model and investigation of adhesion mechanisms", Sensors and Actuators A, 43 (1994), pages 230-238. Adhesion of neighboring structures is mediated by the cleaning liquid, usually referred to as "stiction". [0008] For semiconductor processing, stiction is primarily important during drying steps which usually follow the etching and cleaning steps in semiconductor wafer processing. There, capillary forces induced by the liquid lead to adhesion of adjacent bottom electrodes. The adjacent bottom electrodes remain stuck to each other even after being completely dried, particularly when the adhesion force between the contacting adjacent bottom electrodes is larger than the elastic restoring force of the deformed bottom electrodes. [0009] Exposing wafers to an air-liquid interface during transfer between etching, cleaning and drying process modules is detrimental to obtaining stiction free process performance. Failing to achieve stiction free process performance ultimately results in a low yield of the produced circuits. One potential solution to this problem is to completely avoid wet processing and perform etching steps using gas phase processing, e.g. in a hydrogen fluoride vapor. However, such gas phase processing leads to etching residues and to silicon surface termination states which in turn hinders further processing. SUMMARY OF THE INVENTION [0010] It is an object of the invention to provide a system and corresponding method for fabricating free-standing nanostructures on a semiconductor wafer which overcomes the above mentioned problems associated with stiction. [0011] It is another object of the invention to provide such a system and method that includes etching, cleaning, and drying of a semiconductor wafer with a patterned hard mask layer for fabrication of bottom electrode structures. [0012] The aforesaid objects are achieved individually and in combination in accordance with the present invention, and it is not intended that the present invention be construed as requiring two or more of the objects to be combined unless expressly required by the claims attached hereto. [0013] In accordance with the invention, a method for fabricating and cleaning free-standing nanostructures includes providing a semiconductor wafer comprising a substrate and a patterned layer above the substrate, the patterned layer comprising a plurality of openings extending from an upper surface of the patterned layer to an upper surface of the substrate, and structural elements being arranged within the openings, providing a process chamber, the process chamber being configured to receive the semiconductor wafer, introducing the semiconductor wafer into the process chamber, injecting an etching chemistry into the process chamber to etch the patterned layer and to release the structural elements as free-standing nanostructures on the semiconductor wafer, the etching chemistry comprising a carbon dioxide fluid and an etching solution, injecting a cleaning chemistry into the process chamber in order to remove particles from the surface of structural elements being free-standing nanostructures on the semiconductor wafer, the cleaning chemistry comprising a supercritical carbon-dioxide fluid and cleaning solution, rinsing the semiconductor wafer by flooding a carbon dioxide fluid into the process chamber, and drying the semiconductor wafer by injecting a supercritical carbon dioxide fluid into the process chamber and by venting out the supercritical carbon dioxide fluid from the process chamber. [0014] Accordingly, stiction free processing is achieved by employing unique properties of carbon dioxide in the supercritical or liquid state. The supercritical state is a high density phase characterized by a low viscosity and a zero surface tension, thus enabling better solubility and efficiency of the etching chemistry. On the other hand, properties similar to a gas phase presents high diffusion capabilities, allowing for easy solvent removal and greater drying efficiency. Another feature of the invention is that all process steps are performed in the same process chamber. This ensures that no air-liquid interfaces during transfer between etching, cleaning and drying process modules can occur. Accordingly, capillary forces are eliminated. This is achieved by employing carbon dioxide in its various states, i.e. supercritical, liquid and gas. Furthermore, a cleaning step is applied which removes residues on the surface of the free-standing nanostructures. The cleaning step is performed in the same process chamber thus utilizing a supercritical process sequence which allows for adding a cleaning solution. As a result, contaminants on the surface of the free-standing nanostructures are largely eliminated. [0015] In accordance with another embodiment of the invention, a method for fabricating and cleaning free-standing nanostructures includes providing a semiconductor wafer having a substrate and a patterned layer above the substrate, the patterned layer comprising structural elements as free-standing nanostructures, providing a process chamber, the process chamber being configured to receive the semiconductor wafer, introducing the semiconductor wafer into the process chamber, injecting a cleaning chemistry into the process chamber in order to remove particles from the surface of structural elements being free-standing nanostructures on the semiconductor wafer, the cleaning chemistry comprising a supercritical carbon-dioxide fluid and a cleaning solution, rinsing the semiconductor wafer by flooding a supercritical carbon-dioxide fluid into the process chamber, and drying the semiconductor wafer by venting out the supercritical carbon-dioxide fluid from the process chamber. [0016] In accordance with another embodiment of the invention, a system for fabricating and cleaning free-standing nanostructures comprises: a semiconductor wafer comprising a substrate and a patterned layer disposed above the substrate, the patterned layer comprising a plurality of openings extending from the surface of the patterned layer to the surface of the substrate and structural elements being arranged within the openings; a process chamber, the process chamber being configured to receive the semiconductor wafer; means for introducing the semiconductor wafer into the process chamber; means for injecting an etching chemistry into the process chamber to etch the patterned layer and to release the structural elements as free-standing nanostructures on the semiconductor wafer, the etching chemistry comprising a liquid or supercritical carbon dioxide fluid and an etching solution; means for injecting a cleaning chemistry into the process chamber in order to remove particles from the surface of structural elements being free-standing nanostructures on the semiconductor wafer, the cleaning chemistry comprising a supercritical carbon-dioxide fluid and cleaning solution; means for rinsing the semiconductor wafer by flooding supercritical carbon dioxide fluid into the process chamber; and means for drying the semiconductor wafer by venting out supercritical carbon dioxide fluid from the process chamber. [0017] The above and still further objects, features and advantages of the present invention will become apparent upon consideration of the following definitions, descriptions and descriptive figures of specific embodiments thereof wherein like reference numerals in the various figures are utilized to designate like components. While these descriptions go into specific details of the invention, it should be understood that variations may and do exist and would be apparent to those skilled in the art based on the descriptions herein. BRIEF DESCRIPTION OF THE DRAWINGS [0018] FIG. 1 depicts a side view in partial cross-section of a semiconductor wafer including a plurality of stacked capacitor DRAM-cells. [0019] FIG. 2 depicts a side view in partial cross-section of a semiconductor wafer including a plurality of surrounding gate transistors. Continue reading... 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