| Method and system for detecting a mode of operation of an integrated circuit, and a memory device including same -> Monitor Keywords |
|
|
  Method and system for detecting a mode of operation of an integrated circuit, and a memory device including sameUSPTO Application #: 20060208758Title: Method and system for detecting a mode of operation of an integrated circuit, and a memory device including same Abstract: A threshold detection circuit for developing a mode trigger signal includes an input that receives an input signal. In response to the input signal having approximately an input threshold value for a triggering time, the threshold detection circuit activates the mode trigger signal on an output. In response to the input signal being substantially different from the input threshold value or the input signal not having the input threshold value for the triggering time, the circuit deactivates the mode trigger signal. The threshold detection circuit may be contained in a variety of different mode detection circuits for detecting when an integrated circuit is to be placed in a test mode or other desired mode of operation, and such mode detection circuits may be contained in a variety of different types of integrated circuits, such as memory devices generally and SRAMs specifically. (end of abstract)
Agent: Kimton N. Eng, Esq. Dorsey & Whitney LLP - Settle, WA, US Inventor: Kenneth W. Marr USPTO Applicaton #: 20060208758 - Class: 326016000 (USPTO) The Patent Description & Claims data below is from USPTO Patent Application 20060208758. Brief Patent Description - Full Patent Description - Patent Application Claims
TECHNICAL FIELD [0001] The present invention relates generally to semiconductor integrated circuits, and more specifically to detecting conditions associated with the operation of semiconductor integrated circuits such as memory devices. BACKGROUND OF THE INVENTION [0002] In semiconductor memory devices and other semiconductor integrated circuits, the devices are typically placed in a test mode of operation during manufacture to ensure that the devices operate as required. A variety of different techniques are utilized to place the device in the a particular mode of operation, such as a test mode of operation. For example, in a dynamic random access memory ("DRAM"), a particular sequence of applied control signals may be applied to place the device in the test mode of operation, such as activating a column address strobe signal {overscore (CAS )}before a row address signal {overscore (RAS)}, which does not occur during normal operation of the memory device. Another conventional method for placing a memory device in a test mode of operation is to apply a "supervoltage" to a particular pin of the memory device. The supervoltage has a value greater than the normal operating range of signals applied on the pin, and when circuitry within the memory device senses the supervoltage, the device begins operating in the test mode. [0003] In some situations, however, a particular technology limits the utilization of the supervoltage approach to placing the memory device in the test mode. For example, in a static random access memory ("SRAM"), at least some external pins of the memory typically include diodes coupled between the pin and a supply voltage to provide clamping of signals applied to the pin. FIG. 1 is a functional diagram illustrating an external pin 100 of an SRAM coupled to internal circuitry 102 in the SRAM. A clamping diode 104 is coupled between the external pin and a supply voltage VCC to limit or "clamp" voltages on the external pin 100 and thereby prevent such voltages from damaging the internal circuitry 102. When such diodes 104 are utilized, it is not possible to apply a supervoltage to the external pin 100 to place the SRAM in a test mode of operation since the clamping diode 104 limits the voltage on the external pin to a threshold voltage VT of the diode above the supply voltage VCC. This is true because the clamping diode 104 prevents the voltage on the pin from being driven to a level sufficiently above normal operating levels to allow the internal circuitry 102 to reliably detect the presence of the supervoltage and place the SRAM in the test mode of operation. Moreover, a permissible range of values for the supply voltage VCC may include the value VCC+VT and thus this voltage cannot not be used to place the SRAM in the test mode. [0004] With any technique for placing an integrated circuit in a test mode of operation, it must be extremely unlikely that the test mode can be inadvertently entered by a user of the memory device. It must be extremely unlikely that the test mode will be inadvertently entered because entering the test mode will typically render the device inoperable. For example, in a typical memory device, during the test mode redundant circuits are utilized to replace defective elements in the device. If the test mode of the device is reentered, such redundant elements are typically disabled to allow for testing of the device. Thus, if a customer were to inadvertently enter the test mode, the device would become inoperable since the redundant elements being utilized to replace defective elements in the memory device will be disabled. [0005] There is a need for a reliable technique to place a wide variety of integrated circuits into a test or other desired mode of operation where the use of one or more of the existing approaches is not viable. SUMMARY OF THE INVENTION [0006] According to one aspect of the present invention, a method of detecting a mode of operation of an integrated circuit includes receiving a signal having a first level corresponding to a first logic state and a second level corresponding to a second logic state. The signal has a midpoint being defined between the first and second logic states. The method detects whether the signal is approximately at the midpoint and when the signal is detected at the midpoint, the mode of operation is detected. The detected mode of operation may be a test or other mode of operation of the integrated circuit. BRIEF DESCRIPTION OF THE DRAWINGS [0007] FIG. 1 is a simplified functional diagram of an external pin in a conventional SRAM. [0008] FIG. 2A is a functional block diagram of midpoint detection circuit and output circuit according to one embodiment of the present invention. [0009] FIG. 2B is a signal diagram illustrating a sample of the input signal applied to the midpoint detection circuit of FIG. 2A. [0010] FIG. 3 is a functional block diagram of another embodiment of the midpoint detection circuit 200 of FIG. 2A. [0011] FIG. 4 is a schematic of a threshold detection circuit according to one embodiment of the present invention. [0012] FIG. 5 is a functional block diagram illustrating one embodiment of a test mode detection circuit including a number of the threshold detection circuits of FIG. 4. [0013] FIG. 6 is a functional block diagram illustrating another embodiment of a test mode detection circuit including the threshold detection circuit of FIG. 4. [0014] FIG. 7 is a functional block diagram of a memory device including the test mode detection circuit of FIGS. 5 or 6 and/or the threshold detection circuit of FIGS. 2 and 3 according to one embodiment of the present invention. [0015] FIG. 8 is a functional block diagram of a computer system including the memory device of FIG. 7. DETAILED DESCRIPTION OF THE INVENTION [0016] FIG. 2A is a functional block diagram of a midpoint detection circuit 200 that detects a midpoint MP of an input signal SIN and generates a midpoint signal MS indicating whether the midpoint level has been detected, with the MS signal being utilized to indicate a variety of different conditions such as a specific mode of operation to be entered by an output circuit 202 receiving the MS signal, as will be described in more detail below. A myriad of different types of circuits can receive the MS signal and perform some operation in response to that signal, and in FIG. 2A these circuits are illustrated generically as the output circuit 202 that generates an output signal SOUT responsive to the MS signal. [0017] In the following description, certain details are set forth to provide a sufficient understanding of the present invention, but one skilled in the art will appreciate that the invention may be practiced without these particular details. Furthermore, one skilled in the art will appreciate that the example embodiments described below do not limit the scope of the present invention, and will also understand that various modifications, equivalents, and combinations of the disclosed example embodiments and components of such embodiments are within the scope of the present invention. The operation of well known components has not been shown or described in detail in the following description to avoid unnecessarily obscuring the present invention. [0018] The SIN signal may be any type of signal having a high voltage VH corresponding to a first logic state and a low voltage VL corresponding to a second logic state. The midpoint of the SIN signal detected by the detection circuit 200 is designated MP in the signal diagram of FIG. 2B, and may lie anywhere between the high voltage VH and low voltage VL. Thus, the midpoint MP need not necessarily lie exactly at the half way point between the two voltages (i.e., need not be at (VL+(VH-VL))/2). The significance of the SIN signal being at the midpoint MP may indicate any of a variety of conditions, desirable or undesirable, and the SIN signal may need to remain at the midpoint for a long or short duration depending on the condition being detected by the midpoint detection circuit 200, as will be described in more detail below. [0019] In one embodiment, the midpoint detection circuit 200 is formed by a PMOS transistor 204 and NMOS transistor 206 coupled to form a conventional inverter except that a resistor 208 is coupled between an output node 210 corresponding to the drain of the PMOS transistor and an output node 212 corresponding to the drain of the NMOS transistor. The midpoint signal MS corresponds to the voltage across the resistor 208 and hence across nodes 210/212 in this embodiment. Each of the transistors 204, 206 has an associated threshold voltage VT, and the midpoint MP corresponds to a voltage value where the gate-to-source voltage of each transistor is greater than the associated threshold voltage so that both transistors are turned ON at the same time. In one embodiment of the midpoint detection circuit 200 formed by the transistors 204, 206 and the resistor 208, the circuit operates at 0.5 volts and a current ranging from 200 microamps to 10 milliamps, with the resistor having a value ranging from 50 ohms to 2500 ohms. Continue reading... Full patent description for Method and system for detecting a mode of operation of an integrated circuit, and a memory device including same Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Method and system for detecting a mode of operation of an integrated circuit, and a memory device including same patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. Start now! - Receive info on patent apps like Method and system for detecting a mode of operation of an integrated circuit, and a memory device including same or other areas of interest. ### Previous Patent Application: Method and apparatus for a reliability testing Next Patent Application: Level shifter Industry Class: Electronic digital logic circuitry ### FreshPatents.com Support Thank you for viewing the Method and system for detecting a mode of operation of an integrated circuit, and a memory device including same patent info. IP-related news and info Results in 0.11098 seconds Other interesting Feshpatents.com categories: Software: Finance , AI , Databases , Development , Document , Navigation , Error |
||
