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Method and system for deferred command issuing in a computer systemRelated Patent Categories: Electrical Computers And Digital Data Processing Systems: Input/output, Input/output Data Processing, Input/output Command Process, Operation SchedulingMethod and system for deferred command issuing in a computer system description/claimsThe Patent Description & Claims data below is from USPTO Patent Application 20070088856, Method and system for deferred command issuing in a computer system. Brief Patent Description - Full Patent Description - Patent Application Claims
PRIORITY DATA [0001] This application claims the benefits of U.S. Patent Application Ser. No. 60/727,668, which was filed on Oct. 18, 2005 and entitled "Smart CPU Sync Technology for MultiGPU Solution." CROSS REFERENCE [0002] This application also relates to U.S. patent application entitled "TRANSPARENT MULTI-BUFFERING IN MULTI-GPU GRAPHICS SUBSYSTEM", U.S. patent application entitled "EVENT MEMORY ASSISTED SYNCHRONIZATION IN MULTI-GPU GRAPHICS SUBSYSTEM" and U.S. patent application entitled "METHOD AND SYSTEM FOR SYNCHRONIZING PARALLEL ENGINES IN A GRAPHICS PROCESSING UNIT", all of which are commonly filed on the same day, and which are incorporated by reference in their entirety. BACKGROUND [0003] The present invention relates generally to the synchronization between a computer's central processing units (CPUs) and peripheral processing units, and, more particularly, to the timing of command issuing. [0004] In a modern computer system, each peripheral functional module, such as audio or video, has its own dedicated processing subsystem, and the operations of these subsystems typically require direct control by computer's central processing unit (CPU). Besides, communication and synchronization among components of the subsystems are typically achieved through hardware connections. In an advanced graphics processing subsystem with two or more graphics processing units (GPUs), for instance, a CPU has to frequently evaluate the state of GPUs, and a next rendering command can only be issued when a previous or current command is finished. In other cases, when CPU(s) is calculating something for GPUs using multi-threaded technology, the GPUs may have to wait for the CPU to complete the calculation before executing commands that need the result from CPU(s). When one GPU requests data from another GPU, the transfer must be made through a direct hardware link or the bus, and controlled by the CPU, which then has to wait for the data transfer to complete before executing subsequent commands. Either CPU waiting for GPU or vice versa, the wait time is a waste and lowers the computer's overall performance. [0005] It is therefore desirable for a computer system to be able to detach hard waiting as much as possible from CPU's operations. SUMMARY [0006] In view of the foregoing, this invention provides a method and system to remove some of the wait time by the CPU, as well as some idle time in peripheral processing units. In other words, it increases parallelism between processors. [0007] A method and system are disclosed for employing deferred commands issuing in a computer system with multiple peripheral processors operating with a peripheral device driver embedded in one or more central processor(s). After issuing a first command with a first event tag by the peripheral device driver, a second command is generated for a first peripheral processor by the peripheral device driver following the issuing of the first command. The second command is stored awaiting for the first event tag to be returned, and the second command is issued when the first event tag is returned if the first and second commands need to be synchronized. [0008] The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS [0009] FIG. 1 is a block diagram of a part of a traditional computer system. [0010] FIG. 2 is a block diagram of a part of a computer system according to one embodiment of the invention. [0011] FIG. 3 illustrates commands and event-tag flowing according to one embodiment of the invention. [0012] FIG. 4A is a flow chart showing a command block generating and a synchronization mechanism according to one embodiment of the present invention. [0013] FIGS. 4B and 4C are flow charts illustrating two different driver subroutines within each command block and execution according to one embodiment of the present invention. [0014] FIGS. 5A and 5B are command timing diagrams for showing time saving effects of deferred-command-issuing according to one embodiment of the present invention. DESCRIPTION [0015] Detailed information with regard to the operation of the GPU in the computer system is further described in U.S. patent application entitled "TRANSPARENT MULTI-BUFFERING IN MULTI-GPU GRAPHICS SUBSYSTEM", U.S. patent application entitled "EVENT MEMORY ASSISTED SYNCHRONIZATION IN MULTI-GPU GRAPHICS SUBSYSTEM" and U.S. patent application entitled "METHOD AND SYSTEM FOR SYNCHRONIZING PARALLEL ENGINES IN A GRAPHICS PROCESSING UNIT", all of which are commonly filed on the same day, and which are incorporated by reference in their entirety. [0016] FIG. 1 illustrates a part of a traditional computer system 100. In such a system, a peripheral device driver 110 is just a program, functioning essentially like an instruction manual that provides the operating system with information on how to control and communicate with special processors 120 and 130 of a peripheral subsystem 140. The driver 110 does not have any control function, which is instead carried out by one or more central processor(s) (CPU) 150. Communications between the special processors 120 and 130 take place through hardware connection 160 or through the bus 170. [0017] As an embodiment of present invention, FIG. 2 illustrates a part of a multi-processor computer system 200 with a driver 210 embedded in one or more central processor(s) 220. Here, the `embedded` means that the driver actually runs in the CPU and employs some of the CPU processing capability, so that the driver can generate commands to be stored in the buffer, assign event-tags when synchronizations with other commands are needed, issue the commands and monitor the return of the event-tags, all without CPU hard wait. Such driver implementation does not require extensive hardware support, so it is also cost effective. [0018] The computer system 200 also employs a command buffer 230, which stores immediate commands sent by the driver 210. The command buffer 230 can be just a memory space in a main memory 290 or another memory located anywhere, and can be dynamically allocated by the driver 210. With the processing power of the central processor(s) 220, the driver 210 directs command buffering in and subsequently issuing from the command buffer 230, as well as synchronization among special processors 240 and 250 and the central processor(s) 220. The special processors can be processors dedicated for graphics operations, known as graphics processing units (GPUs). Continue reading about Method and system for deferred command issuing in a computer system... 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