| Method and structure in the manufacture of mask read only memory -> Monitor Keywords |
|
|
  Method and structure in the manufacture of mask read only memoryUSPTO Application #: 20060199339Title: Method and structure in the manufacture of mask read only memory Abstract: A method and structure of manufacture of mask ROM device is provided. Firstly, a semiconductor structure is provided that comprises a first dielectric layer, a plurality of buried bit lines and a plurality of code areas, wherein each of the code areas is placed between two buried bit lines. Next, a second dielectric layer having a plurality of contact plugs is formed on the semiconductor structure, wherein the contact plug comprises a second dielectric layer and a first glue layer, furthermore; the first glue layer is placed on the side-wall and bottom of the contact plugs. In addition, the contact plugs filled with the first metal layer. Then, a second glue layer, a second metal layer and a pad layer having an opening pattern are respectively formed on the second dielectric layer and contact plug. Thus, the processes of the present invention can improve the stability and accuracy in the electricity of the mask ROM device. (end of abstract) Agent: Squire, Sanders & Dempsey L.l.p - Palo Alto, CA, US Inventors: Lawrence Liu, Yuan Kao USPTO Applicaton #: 20060199339 - Class: 438275000 (USPTO) Related Patent Categories: Semiconductor Device Manufacturing: Process, Making Field Effect Device Having Pair Of Active Regions Separated By Gate Structure By Formation Or Alteration Of Semiconductive Active Regions, Having Insulated Gate (e.g., Igfet, Misfet, Mosfet, Etc.), Making Plural Insulated Gate Field Effect Transistors Of Differing Electrical Characteristics The Patent Description & Claims data below is from USPTO Patent Application 20060199339. Brief Patent Description - Full Patent Description - Patent Application Claims
PRIORITY REFERENCE TO RELATED APPLICATION [0001] This application is a divisional of, claims priority to, and incorporates by reference U.S. patent application Ser. No. 10/807,795 filed Mar. 23, 2004 and entitled "Method and Structure in the Manufacture of Mask Read Only Memory." BACKGROUND OF THE INVENTION [0002] 1. Field of the Invention [0003] This invention relates to a method and structure in the manufacture of semiconductor memory devices, and more particularly to method and structure of manufacture of mask ROM memory devices. [0004] 2. Description of the Prior Art [0005] A memory device is widely used in the information industry, and is particularly used in microprocessors and computers. In order to achieve a faster speed of information exchange with a tremendous quantity, the information product needs the properties that are necessarily small in size and a reduced weight. Besides, the program and operation performed the software has become complicated in the recent years so that the properties are necessarily manufacturing a memory with a higher memory capacity and faster access speed. Therefore, a mask ROM with higher memory capacity, higher integrity and faster access speed is currently a common memory structure. [0006] However, when the dimension of the mask ROM device goes below 0.35 microns or smaller, a gap between 0 to 1 has become smaller in the electricity because of the device margin and narrower line width. Hence, the demanded process window is also getting smaller. When the process with the bigger dimension of the device is completely imitated to a smaller dimension, it could not get a preferred yield due to different properties and different structure with Inter-Layer Dielectric (ILD) between two products. [0007] FIG. 1A to FIG. 1D is the method and structure of manufacture in conventional mask ROM memory devices 100. Referring to FIG. 1A, providing a semiconductor substrate 101 firstly, such as P type silicon substrate, wherein the semiconductor substrate 101 comprises a plurality of buried N+ bit lines 103 therein. Next, a gate oxide layer 105 and a plurality of polysilicon word lines 107 are respectively formed on the semiconductor substrate 101. Then, an inter layer dielectric 109, the material could be Borophosphosilicate Glass (BPSG), is formed on the polysilicon word lines 107. After that, forming a glue layer 111 on the inter layer dielectric 109. [0008] Following that, referring to FIG.1B, forming a photoresist layer 113 on the glue layer 111, and performing a photolithography and etching process to the photoresist layer 113 in order to form a first opening 112 therein. The photoresist layer 113 having a first opening 112 is formed on the surface of the glue layer 111. [0009] Subsequently, referring to FIG. 1C, utilizing the photoresist layer 113 having a first opening 112 as a photomask and then performing a dry etching process in the glue layer 111. Therefore, the second opening 115 are formed on the surface of the inter layer dielectric (ILD) 109 and within the glue layer 111. Next, removing the photoresist layer 113. Then, performing a step of ion implantation 117 in the mask ROM device 100 so as to form the code areas 119 within the semiconductor substrate 101. [0010] Continue referring to FIG. 1C, as a result it has to etch the glue layer 111 before forming the code areas 119 in the mask ROM device 100, though the inter layer dielectric 109 which is an oxide layer below the glue layer 111. Hence, etching the glue layer 111 will have a phenomenon of over etching within the inter layer dielectric 109, which could not precisely control the thickness of the inter layer dielectric 109 after each etching. Moreover, the etching process will also produce a profile with bevels in the inter layer dielectric 109. For that reason; the phenomenon of over etching and the profile with bevels in the inter layer dielectric 109 will influence the implanted profile and implanted depth of the code areas 119 in the semiconductor substrate 101 when ion implanting in the mask ROM device 100. Also, the threshold voltage of the mask ROM device 100 is decided by the implanted ion concentration so that the profile with bevels and the phenomenon of over etching will cause the implanted ion distribute non-uniformly. Therefore, it causes the electricity unstably in the mask ROM device 100; moreover, the yield will also be influenced. [0011] In addition, due to the fact that the etching process to the mask ROM device 100 is performed first, and then the implantation of ROM code, which decides the order-form from the users. However, the second opening 115 is accessible to oxidize so as to form an oxide layer on the surface while waiting for an order-form. (Because the bottom of the second opening 115 is an inter layer dielectric 109) Therefore, after receiving the order-form from users, it has to perform an etching or cleaning process to the second opening 115 so as to remove the oxide layer, which is formed already. Then, performing the ion implantation following that, so the manufacturing time and manufacturing cost will be improved. [0012] Still, after accomplishing the etching process to the glue layer 111, the second opening 115 produced therein has a negative bias with a critical dimension. Thus, in order to maintain the critical dimensional after the etch inspection as the same as the photomasks critical dimensional after etching the glue layer 111 (it means to broaden the code areas 119), the post exposure process of the photoresist layer 113 has to be preformed when doing the photolithography process. However, the patterned photoresist layer and the non-patterned photoresist layer are exited simultaneously on the photoresist layer 113 (the patterned photoresist layer with respects to the implant region, the non-patterned photoresist layer with respects to the non-implant region). Therefore, the process window of the photoresist layer, which is above the non-implant region will be influenced and reduced, even vanished during the post exposure process. This situation will make the device 10 inaccurate with electricity. [0013] Finally, referring to FIG. 1D, utilizing a sputtering method to form a blanket layer of metal 121, which uses as an electric connection with the polysilicon word lines 107, on the mask ROM device 100 and down to the code areas 119. [0014] As mentioned above the process of the conventional mask ROM, the conventional mask ROM device has problems with inaccuracy and unstability in the electricity because etching the glue layer and post exposing to the photoresist layer. Hence, a method of manufacture of mask ROM memory devices is required to overcome the problems of the process in the prior art. SUMMARY OF THE INVENTION [0015] It is an objective of the present invention to provide a method and structure in the manufacture of a mask ROM(read only memory) device that utilizes a step of blanket etching back to the first glue layer so that the phenomenon of over etching is not produced in the second dielectric layer. It means that the profile of the implanted depth will not be influenced by over etching. Hence, the stability of the device will be enhanced and have a good yield. [0016] It is another objective of the present invention to provide a method and structure in the manufacture of a mask ROM device that directly defines the critical dimension of the second opening on the photoresist layer that the post exposing process is not necessary to perform. Therefore, the accuracy of the device is improved. [0017] It is a further objective of the present invention to provide a method and structure in the manufacture of a mask ROM device that deposits a first metal layer on a first glue layer. However, the steps of planarizing the first metal layer and forming the code areas in the mask ROM device wait until receiving the order-form from a user so that the second dielectric is not oxidized while waiting on an order-form. Hence, the manufacturing time and manufacturing cost will be reduced. [0018] According to a preferred embodiment of the present invention, a method and structure of manufacture of mask ROM device is provided. Firstly, a semiconductor structure comprises a first dielectric layer thereon, a plurality of buried bit lines and a plurality of code areas, wherein each of the plurality of code areas are placed between two of plurality of the buried bit lines therein. Next, a second dielectric layer having a plurality of contact plugs is formed on the semiconductor structure. Furthermore; the first glue layer is placed on the side-wall and bottom of the contact plug. In addition, the contact plug filled with the first metal layer. Then, a second glue layer, a second metal layer and a pad layer with an opening pattern are sequentially formed on the second dielectric layer and contact plug. BRIEF DESCRIPTION OF THE DRAWINGS [0019] The objectives and features of the present inventions as well as advantages thereof will become apparent from the following detailed description, considered in conjunction with the accompanying drawings. It is to be understood, however, that the drawings, which are not to scale, are designed for the purpose of illustration and not as a definition of the limits of the invention, for which reference should be made to the appended claims. [0020] The present invention can be the best understood through the following description and accompanying drawings, wherein: Continue reading... Full patent description for Method and structure in the manufacture of mask read only memory Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Method and structure in the manufacture of mask read only memory patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. Start now! - Receive info on patent apps like Method and structure in the manufacture of mask read only memory or other areas of interest. ### Previous Patent Application: Atomic layer deposition of metal oxide and/or low asymmetrical tunnel barrier interpoly insulators Next Patent Application: Methods of forming threshold voltage implant regions Industry Class: Semiconductor device manufacturing: process ### FreshPatents.com Support Thank you for viewing the Method and structure in the manufacture of mask read only memory patent info. IP-related news and info Results in 0.62048 seconds Other interesting Feshpatents.com categories: Medical: Surgery , Surgery(2) , Surgery(3) , Drug , Drug(2) , Prosthesis , Dentistry |
||
