| Method and process for improved uniformity of electrochemical plating films produced in semiconductor device processing -> Monitor Keywords |
|
|
  Method and process for improved uniformity of electrochemical plating films produced in semiconductor device processingUSPTO Application #: 20060226014Title: Method and process for improved uniformity of electrochemical plating films produced in semiconductor device processing Abstract: A method and device for ECP copper deposition into openings and over a surface of a semiconductor substrate provides a final deposited film with a uniform height across the substrate. The substrate is submerged in an ECP electrolyte solution with accelerants formed on a dielectric surface and in and over damascene openings formed in the dielectric surface, and copper is deposited onto the surface and into the damascene openings. A deplating process that uses a reverse polarity of power conditions used in the ECP process is then used for a brief time to remove some of the deposited copper and an excess portion of the accelerant. The copper is preferentially removed from portions where the initial deposition produced localized thick portions and the deplating process is followed by a further ECP process that yields a copper film with a uniform top surface. (end of abstract) Agent: Howard Chen Preston Gates & Ellis LLP - San Francisco, CA, US Inventors: Yen Chuang, Huang-Yi Huang USPTO Applicaton #: 20060226014 - Class: 205087000 (USPTO) Related Patent Categories: Electrolysis: Processes, Compositions Used Therein, And Methods Of Preparing The Compositions, Electrolytic Coating (process, Composition And Method Of Preparing Composition), Simultaneous Deplating And Plating The Patent Description & Claims data below is from USPTO Patent Application 20060226014. Brief Patent Description - Full Patent Description - Patent Application Claims
BACKGROUND [0001] The present invention relates generally to the electrochemical plating of film and more particularly to the electrochemical plating of copper-based metal layers during the fabrication of semiconductor devices. [0002] In the fabrication of integrated circuit (IC) semiconductor devices, substrate surface planarity is of critical importance. This is especially so as the scale of integration increases and the device features are reduced in size (e.g., sub-micron sized geometries). ICs typically include metal layers that are used to interconnect individual device features thereof. Individual metal layers are typically isolated from each other by one or more insulating, dielectric material layers. Conductive interconnection features (e.g., trenches, vias, contacts, etc.) may be formed through the dielectric layers to provide the electrical access between successive conductive metal layers. [0003] Copper and copper alloys are becoming a metal of choice in ICs as the metal layers and the interconnection structures that provide the electrical access between successive metal layers. Copper metal is used because its material properties feature lower resistance and improved electromigration performance compared to traditional metal materials such as aluminum and aluminum alloys. Copper and copper alloy layers (films) may be deposited by various methods such as physical vapor deposition (PVD), chemical vapor deposition (CVD) and electrochemical plating (ECP). ECP for copper is preferred as a low cost and effective deposition method. A typical ECP process for copper involves the deposition of the metal conductive layer on the semiconductor substrate surface by contacting the wafer with an electrolyte solution and applying an electrochemical potential between electrodes of opposing polarities. During this process, copper ions plate out of the electrolyte solution and deposit onto the semiconductor substrate surface. [0004] Copper is typically difficult to pattern and etch. Accordingly, copper features are typically formed using a damascene or dual damascene processes. In damascene processes, features such as vias and/or trenches, are defined within the dielectric material and subsequently filled with copper. The copper is deposited both into the opening in the dielectric feature and onto the surrounding field on top of the dielectric layer. The copper deposited onto the field may be subsequently removed to leave the copper filled feature formed within the dielectric or reduced, left on to become subsequently patterned and etched to become the next metal line layer of the IC device. [0005] The copper or copper alloy film deposited on the field (top of the dielectric) may be removed or planarized by using such methods as chemical mechanical polishing (CMP), plasma etching and or wet etching. Copper film removal and planarization difficulties are dependant upon the thickness uniformity of the copper layer. The ECP processes may not produce copper metal layers of uniform thickness on top of the dielectric layer, particularly at and near the field locations above the copper-filled via and/or trench features within the dielectric layer. At these field locations, above the copper-filled vias and/or trenches, the deposited copper layer thickness is usually greater than the rest of the field due to an accelerated rate of copper deposition (ECP activity) at that particular field region. This accelerated deposition rate is attributed to excess electrochemical activity resulting from the copper deposition of the underlying via and/or trench features. [0006] FIG. 1 illustrates the phenomena of non-uniform thickness deposition during the conventional ECP processing of areas over underlying via/trench type structures and areas with no underlying structures. FIG. 1A is a cross-section of a portion of an IC semiconductor device 100 during fabrication. The dielectric substrate 102 is shown with several damascene via/trench structures 104 having been fabricated into the dielectric substrate 102. These via/trench structures 104 have been fabricated so that subsequent ECP processing will deposit a copper based metal film both over the dielectric and into the structures 104, filling them to completion with continued deposition to obtain a desired thickness of the copper based film onto the surrounding field on top of the dielectric substrate 102. The positions of the black dots 106 of the figure represent the relative concentration and distribution of the active accelerant component of the ECP chemicals that are used for the deposition process. It is noted that the distribution of the ECP accelerant 106 is fairly evenly distributed across the multi-dimensioned open surface of the dielectric 102 at the start of the actual ECP deposition, both across the top of the field and within the open damascene via/trench structures 104. [0007] FIG. 1B illustrates how the previously even distribution of the ECP accelerant 106 changes as the via/trench structures 104 are filled during the ECP process. As the via/trench structures 104 are filled, the ECP accelerants 106 that were located within these open structures migrate upwards. The resultant migration of the ECP accelerants 106 produces a non-uniform distribution of the ECP accelerants 106 across the changing top surface of the open dielectric substrate 102. It is this excess and uneven distribution of the ECP accelerant 106 during the ECP deposition processing that causes the non-uniform final thickness of a deposited copper-based film 108. FIG. 1C illustrates the final non-uniformity of the copper-based film 108. The final copper metal film 108 is shown on top of the dielectric substrate 102. The thickness of the copper film 108 over the dielectric substrate 102 areas without any underlying via/trench structures 104 is generally consistent and uniform. However, the thickness of the copper film portion 110 located above the underlying, filled via/trench structures 104 is significantly thicker than the surrounding field areas without any underlying via/trench structures. This increased copper thickness region 110 corresponds to the locations of higher concentration, excess ECP accelerants 106 that were shown in FIG. 1B. [0008] In addition to the previously discussed micro non-uniformity issue related to structures within the dielectric layers, a macro copper layer uniformity problem may occur across the entire wafer substrate by which the IC devices are built upon. Various dispersion and non-uniformity issues of the ECP chemicals (e.g., accelerants) affected by various mechanical and equipment related factors may cause the wafers to experience a thickness variation from wafer edge to wafer center. In typical ECP processing of semiconductor wafers, the wafer center tends to experience a higher rate of copper metal deposition than the wafer edge, thus often producing wafers with the copper metal layers thicker at the center versus the edge. The graph of FIG. 2 illustrates the typical relationship of final plating thickness, shown as the y-axis of the graph, as a function of the process wafer location, shown as the x-axis of the graph. The graph shows the typical relationship with wafer center locations having an overall thicker final film thickness at locations at the wafer edge. [0009] Typical IC fabrication flows commonly address the micro uniformity issue of the copper layer thickness non-uniformity on top of the field (dielectric) above the regions with light versus dense underlying via/trench features by simply depositing a thick copper film and then relying upon a long and carefully controlled metal planarization/etching process to obtain a flat final copper metal layer. This method of deposition and planarization/etching undesirably adds processing time, wastes copper and is dependant upon tight controls of the planarization/etching processes. Such waste and strict control requirements increase the ICs' fabrication costs and cycle times, as well as the decrease of IC production throughput rates. The macro non-uniformity issue of the copper layer thickness across the wafer areas (center versus edge) may be minimized with careful optimization and control of machine process parameters such as wafer revolution speed during the ECP process. The varying of process parameters during the ECP deposition may undesirably induce film composition variations within the final copper metal film. In addition, the varying values of the process parameters may be more difficult to monitor and control. Despite the implementation of such optimizations to the machine/process parameters, the desired level of the copper layer thickness, uniformity, planarity and composition may still not be obtained. [0010] What is desired is an improved method by which the copper metal layer deposited during the ECP processing is planar as formed, i.e., it includes uniform thickness both over the various topography and fields of the individual IC devices, as well as throughout the semiconductor wafer that includes many IC devices. SUMMARY [0011] In view of the foregoing, this disclosure provides an improved method and process for the ECP deposition of copper metal layers upon a semiconductor substrate surface such that the final deposited film is planar across the semiconductor wafer. [0012] According to one aspect, accelerants are deposited onto the top surface of a dielectric substrate having one or more damascene structures, and the dielectric substrate submerged in an electrolyte. Copper is then deposited onto the top surface of the dielectric substrate and filling the one or more damascene structures and coating a portion of the dielectric substrate. The copper is then deplated for a predetermined period of time to remove an excess portion of the accelerant and a portion of the copper to yield a uniform top surface of the copper. [0013] The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS [0014] FIGS. 1A through 1C are cross-sectional views of a conventional IC device during conventional ECP deposition processing. [0015] FIG. 2 is a graph showing the relationship between final plating thickness and the plating location within the processed wafer for the conventional ECP deposition process. [0016] FIGS. 3A through 3D are cross-sectional views of an IC device during ECP deposition processing using the ideal method and process in accordance with one embodiment of the present invention. [0017] FIG. 4 is a flow chart summarizing the ECP method and processing steps as described in accordance with an embodiment of the present invention. DESCRIPTION [0018] The present disclosure provides a detailed description of an improved method and process for the ECP deposition of copper metal layers upon a semiconductor substrate surface such that the final deposited film is planar and uniform both at the micro uniformity scale, across the various topography and fields of the individual IC devices, as well the macro uniformity scale, across the semiconductor wafer of many IC devices. The improved method and process implements a deplating step, in-situ within the ECP processing, such that excess chemical accelerant components of the ECP chemistry are removed leaving a uniform, even distribution of the components to provide a uniform, planar final deposited copper metal film layer. [0019] FIG. 3 illustrates an exemplary method and process of the present invention. FIG. 3A is a cross-section of a portion of an IC semiconductor device 300 during fabrication. The dielectric substrate 302 is shown with several damascene via/trench structures 304 having been fabricated into the dielectric substrate 302. These via/trench structures 304 have been fabricated so that subsequent ECP processing will deposit a copper based metal film both into the structures 304, filling them to completion with continued deposition to obtain a desired thickness of the copper based film onto the surrounding field on top of the dielectric substrate 302. The positions of the black dots 306 of the figure represent the relative concentration and distribution of the active accelerant component of the ECP chemicals that are used for the deposition process. The accelerants are advantageously included as a component of the ECP electrolyte solution. Accelerants commonly used in the ECP of copper include bis(3-sulfopropyl)disulfide, mercapto-propane-sulfonic acid and thiourea. It is noted that the distribution of the ECP accelerant 306 is fairly evenly distributed across the multi-dimensioned open surface of the dielectric 302 at the start of the actual ECP deposition, both across the top of the field and within the open damascene via/trench structures 304. [0020] FIG. 3B illustrates how the previously even distribution of the ECP accelerant 306 changes as the via/trench structures 304 are filled during the ECP process. As the via/trench structures 304 are filled, the accelerants 306 that were located within these open structures migrate upwards. The resultant migration of the ECP accelerants produces a non-uniform distribution of the accelerants 306 across the changing top surface of the open dielectric substrate 302. It is this excess of accelerants over the via/trench structures 304 and the uneven distribution of ECP accelerant 306 during the ECP deposition processing that would cause the non-uniform final thickness of the deposited copper-based film 308 using conventional methods. The method and process of the present invention provides for the ECP deposition to halt at or near the point at which the damascene via/trench structures 304 are filled and before the bulk deposition of the copper film onto the remaining field areas of the open dielectric substrate 302 begins. A thin copper metal film 308 may be depositing on the remaining field of the open dielectric substrate 302 (shown in FIG. 3B) during the ECP deposition step that fills the via/trench structures 304 in various exemplary embodiments. Continue reading... Full patent description for Method and process for improved uniformity of electrochemical plating films produced in semiconductor device processing Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Method and process for improved uniformity of electrochemical plating films produced in semiconductor device processing patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. Start now! - Receive info on patent apps like Method and process for improved uniformity of electrochemical plating films produced in semiconductor device processing or other areas of interest. ### Previous Patent Application: Manipulation of objects with fluid droplets Next Patent Application: Method of forming electrically isolated structures using thin dielectric coatings Industry Class: Electrolysis: processes, compositions used therein, and methods of preparing the compositions ### FreshPatents.com Support Thank you for viewing the Method and process for improved uniformity of electrochemical plating films produced in semiconductor device processing patent info. IP-related news and info Results in 1.29618 seconds Other interesting Feshpatents.com categories: Electronics: Semiconductor , Audio , Illumination , Connectors , Crypto , |
||
