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  Method and manufacturing low leakage mosfets and finfetsUSPTO Application #: 20070228425Title: Method and manufacturing low leakage mosfets and finfets Abstract: By aligning the primary flat of a wafer with a (100) plane rather than a (110) plane, devices can be formed with primary currents flowing along the (100) plane. In this case, the device will intersect the (111) plane at approximately 54.7 degrees. This intersect angle significantly reduces stress propagation/relief along the (111) direction and consequently reduces defects as well as leakage and parasitic currents. The leakage current reduction is a direct consequence of the change in the dislocation length required to short the source-drain junction. By using this technique the leakage current is reduced by up to two orders of magnitude for an N-channel CMOS device. (end of abstract)
Agent: Schneck & Schneck - San Jose, CA, US Inventors: Gayle W. Miller, Volker Dudek, Michael Graf USPTO Applicaton #: 20070228425 - Class: 257288000 (USPTO) Related Patent Categories: Active Solid-state Devices (e.g., Transistors, Solid-state Diodes), Field Effect Device, Having Insulated Electrode (e.g., Mosfet, Mos Diode) The Patent Description & Claims data below is from USPTO Patent Application 20070228425. Brief Patent Description - Full Patent Description - Patent Application Claims
FIELD OF THE INVENTION [0001] The present invention relates to the fabrication of integrated circuits and, more specifically, a method for fabricating field effect transistors (FETs) wherein source-drain current flows along a (100) crystal plane. BACKGROUND [0002] Semiconductor integrated circuit chips are constructed as dice on wafers. A typical wafer material is crystalline silicon. Wafers are cut from single crystal silicon ingots grown from polysilicon by means of, for example, Czochralski method (CZ) crystal growth. CZ wafers are preferred for VLSI applications as they can withstand high thermal stresses and are able to offer an internal gettering mechanism that can remove unwanted impurities from device structures on a wafer surface. This also gives the wafer a uniform internal structure based on silicon's diamond cubic lattice structure. Although the diamond cubic lattice provides strength and rigidity to the wafer, defects in the crystal lattice, for example, slip dislocations, can adversely affect fabricated circuit electrical properties leading to a reduction in the number of good dice per wafer. A schematic representation of the diamond cubic lattice structure of silicon is depicted in FIG. 1A. [0003] The atoms in a crystal lattice structure of a silicon wafer align with each other to form planes traversing the wafer in multiple directions. Three principal planes, and their respective orientations, (100), (110), and (111), are shown in FIGS. 1B-1D. Equivalent planes are designated by braces, for example, {111}, {110}, and {100}, represent equivalents to the (111), (110), and (100) principal planes, respectively. In many applications, orienting the crystal to an equivalent plane will achieve the same result as aligning it to its principal plane. Many structural properties of silicon depend on its planar orientation. Plane (111) has the highest number of atoms per unit of surface area and is said to be packed very tightly. This high atomic density results in a greater number of available charge carriers, which allows for faster current propagation. Concurrently, the more tightly a crystal plane is packed, the higher the probability that slip dislocations and other defects will occur. These defects can cause parasitic currents as well as charge leaks that can lead to poor performance and device failure. [0004] To help identify crystalline planes, wafers are typically fabricated with a notch or flat relative to a selected crystalline plane. Throughout the integrated circuit (IC) manufacturing industry, automated wafer handling equipment utilize these notches or flats, fabricated in the wafers, to align the wafer, allowing devices on a wafer to be aligned with a specific crystal plane. A development in the art has been the shift to formation of semiconductor devices on a silicon wafer wherein the devices are aligned so that source-drain current in those devices travel along a {110} plane, usually the (110) plane. As indicated above, a {110} plane has a more closely packed atomic structure than a {100} plane, which coincides with a higher charge mobility in devices aligned such that current flows along the (110) plane, as compared to devices aligned such that current flows along the (100) plane. A result of this characteristic of silicon crystals is faster data throughput where device current is aligned along the (110) plane. Several U.S. patents teach the alignment of devices to a (110) plane, for example, U.S. Pat. No. 5,729,045, to Buynosik, entitled "Field Effect Transistor With Higher Mobility," discloses a method of increasing the performance of an FET by aligning channel current with the (110) crystal plane of a (100) wafer. However, the Buynosik device is inappropriate for contemporary high-density device fabrication since any defects present in the crystal lattice can have severe deleterious effects on an electronic device. Buynosik teaches neither how to eliminate or deal with the lattice defects. [0005] In fact, an ongoing trend in microelectronics devices is a reduction in device size. Concurrently, with the scaling down of IC devices, device current paths are smaller and device currents are decreased. One result is that crystal defects and unintentional currents are proportionally larger as IC devices become smaller. [0006] One approach to reducing the problems associated with the defects discussed above is to improve the quality of the wafer itself. One method of improving the wafer is through an epitaxial deposition wherein a thin layer of single crystal silicon material is deposited on the surface of a silicon crystal substrate. These wafers are commonly known as epi wafers. Experimentation has shown that these types of wafers have higher yields than standard wafers. [0007] In FIG. 2, a silicon wafer 201 is shown with a single MOSFET device including a source 205, a drain 207, and a gate 209, wherein a source-drain current channel is aligned to a primary flat 203. The primary flat is typically aligned with the (110) plane and the arrow (vector) indicates a [110] direction, which is normal to the (110) plane. Most commercially available epitaxial wafers are manufactured with the primary flat aligned with the (110) plane. Traditionally, fabrication equipment aligns a wafer using a primary flat (or notch) as a reference. With a primary flat aligned with a (110) plane, devices constructed from these epitaxial wafers have current channels that are aligned along the (110) plane. With larger scale devices, this has not been a problem since any defects formed had little influence on device performance and could be ignored. However, with design rules ever decreasing, any defects present in the crystal lattice can start to have severe deleterious effects on an electronic device. SUMMARY [0008] By aligning the primary flat (or notch) of, for example, an epi wafer with a (100) plane rather than a (110) plane, devices can be formed with primary currents flowing along the (100) plane. In this case, the device will intersect the (111) plane at approximately 54.7 degrees. This intersect angle significantly reduces stress propagation/relief along the (111) direction and consequently reduces defects as well as leakage and parasitic currents. Leakage current reduction is a direct consequence of the change in the dislocation length required to short the source-drain junction. By using this technique, the leakage current is reduced by up to two orders of magnitude for an n-channel CMOS device. [0009] Defects, such as slip dislocation and gettering points for impurities, are also reduced by employing the techniques presented herein. [0010] One application of an embodiment of the present invention relates to the fabrication of metal-oxide-semiconductor field effect transistors (MOSFETs). MOSFET technology is a dominant electronic device technology in use today. Performance enhancement between generations of devices is generally achieved by reducing an overall size of the device, resulting in an enhancement in device speed. This size reduction is generally referred to as device scaling. As MOSFETs are scaled to channel lengths below about 200 nm, conventional MOSFETs suffer from several problems. [0011] An improvement in MOSFET performance and yield has been observed by incorporating the present invention into the MOSFET fabrication process. By aligning the MOSFET channel so that source-drain channel current flows in the (100) plane, manufacturing related defects and related leakage and parasitic currents are reduced. Another application of various embodiments of the present invention is in the fabrication of a specific type of MOSFET device called a FinFET. A FinFET is a MOSFET with a raised current channel (fin) that utilizes a gate electrode on at least three sides of the channel. Aligning the fin with the (100) plane results in a reduction in capacitance between the gate electrode and FinFET channel and body, and superior electrical isolation between the gate electrode and FinFET channel and body. A further benefit of this fabrication method utilizing a (100) channel direction is that the corners of the gate electrode are inherently rounded, reducing local electric fields and consequently increasing the breakdown voltage and improving uniformity of an electric field in a gate dielectric. Additionally, the (100) channel direction fabrication method described herein reduces stress in silicon "corners." This benefit is especially pronounced during high temperature processing (e.g., during growth of a thermal silicon dioxide gate dielectric). One result of the reduction in stress is that, for example, less boron p-type doping atoms diffuse out of corner regions into any adjacent existing oxide or growing oxide. There is thus less segregation of the boron into the silicon dioxide. Silicon corner regions maintain a higher doping concentration and, hence, a higher MOS threshold voltage for formation of a parasitic channel in the finished device. Reduction or elimination in the formation of the parasitic channel at low MOS gate voltages produces a substantial reduction in leakage current of the device. [0012] Concepts and techniques discussed herein may be added to various electronic devices as a mechanism by which leakage current is reduced. A skilled artisan will recognize that the present invention may be incorporated into other embodiments where parasitic device current, defects, and leakage current reduction is desired. BRIEF DESCRIPTION OF THE DRAWINGS [0013] FIG. 1A shows a schematic of a unit cell for a diamond cubic lattice crystal as known in the prior art. [0014] FIGS. 1B-1D show various crystal plane orientations as known in the prior art. [0015] FIG. 2 shows prior art alignment of a primary flat and device orientation on a commercially available epitaxial wafer. [0016] FIG. 3 shows the alignment of a primary flat and device orientation on a wafer with a (100) primary flat orientation. [0017] FIGS. 4A-4O show exemplary process steps for one embodiment of the present invention. [0018] FIGS. 5A-5I show exemplary process steps for another embodiment of the present invention. [0019] FIGS. 6A-6K show an exemplary FinFET device fabricated using various process steps of various embodiments of the present invention. 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