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Method and apparatus to implement a reset function in a non-volatile static random access memory

Method and apparatus to implement a reset function in a non-volatile static random access memory description/claims

1. Field of the Invention

The present invention is generally directed to memory, and more particularly to implementing a reset function in a non-volatile Static Random Access Memory (nvSRAM) cell or array.

2. The Relevant Technology

Semiconductor memory devices are widely used in the computer and electronics industries as a means for retaining digital information. A typical semiconductor memory device is comprised of a large number of memory elements, known as memory cells, that are each capable of storing a single digital bit. The memory cells are arranged into a plurality of separately addressable memory locations, each being capable of storing a predetermined number of digital data bits. All of the memory cells in the device are generally located upon a single semiconductor chip which is contacted and packaged for easy insertion into a computer system.

The issue of producing a resettable semiconductor memory, which involves using a single command to write all “0”s or all “1”s into every memory location, has been frequently discussed. The most straightforward design approach to achieve this in an SRAM is to bring all word lines high, which consequently requires a significant amount of design and silicon overhead to control the very high current surges associated with moving large values of capacitance. Other methods have been employed using flags to output a high or low state when a given section of memory is addressed. In such devices, the individual memory cells are not immediately altered. Particular methods of resetting semiconductor memory are described in U.S. Pat. No. 5,212,663 to Leong, et al. and in U.S. Pat. No. 6,038,176 to Shyn et al.

It would therefore be advantageous to provide a method and apparatus for producing a resettable semiconductor memory without utilizing additional silicon overhead and without providing additional circuitry to control the maximum chip current.

The following embodiments and aspects thereof are described and illustrated in conjunction with systems, tools and methods which are meant to be exemplary and illustrative, not limiting in scope. In various embodiments, one or more of the above-described problems have been reduced or eliminated, while other embodiments are directed to other improvements.

In one embodiment, a method for resetting a semiconductor memory array having a plurality of semiconductor memory cells is provided. Each semiconductor memory cell has at least a volatile memory cell having a bit line pair with a first bit line and a second bit line. The first bit lines of each semiconductor memory in a column of the array are coupled together and the second bit lines are coupled together. The first and second bit lines are connected to an array reset circuit for independently grounding and applying voltage to the first and second bit lines. A node supplying power to each of the volatile memory cells is grounded by connecting the node to a ground node for each of the cells where the ground node has a means for limiting current flowing through the ground node coupled to the volatile memory cell ground node and a main ground node. The means for limiting current is set to a predetermined current limit.

The first bit line of the bit line pair is grounded independent of the second bit line in each column in the array using an array reset circuit. A column of volatile memory cells in the semiconductor memory array is connected to an array reset circuit that is configured to both ground and apply voltage to the first bit line independent of the second bit line. A voltage representing a high state is then applied to each of the second bit lines of the bit line pairs in the semiconductor memory array. A voltage representing a high state is applied to the word line coupled to the volatile memory cell. The supply node from the ground node for each of the volatile memory cells and a voltage representing a high state is applied to the supply node thereby removing the current limit between the node supplying power and the volatile memory cell ground node.

In another embodiment, a semiconductor memory reset for use with a semiconductor memory cell is provided. The reset comprises a circuit with a number of transistors for use with a semiconductor memory cell having a volatile cell and a non-volatile cell. The non-volatile cell is coupled to the volatile cell to transmit a bit of data there between. The volatile cell is configured to receive a bit of data from an exterior source, retain a bit of data and transmit a bit of data to said exterior source. The volatile cell loses a retained bit of data when power is removed from said volatile cell. The non-volatile cell also comprises a first and second transistor trigate structure having a number of series connected transistors, each trigate strucure coupled to the volatile cell. Each trigate has a store transistor, a recall transistor and a memory transistor. When storing data, one transistor trigate is configured as an erase trigate and the other transistor trigate is configured as a store trigate. The store transistors are configured for connecting and disconnecting the non-volatile cell from said volatile cell. The recall transistors are configured for connecting and disconnecting said non-volatile cell from a power source. The memory transistors are configured for storing a bit of data received from the volatile cell and transmitting a bit of data to the volatile memory cell. The reset also comprises a current limiting means coupled to a ground node of the memory cell where the current limiting means is configured for limiting the flow of current from the volatile memory cell to the memory ground node. The reset also has an array reset circuit coupled to a bit line pair of the volatile memory. The array reset circuit is configured for independently controlling the voltage applied to each bit line in said bit line pair.

In addition to the exemplary aspects and embodiments described above, further aspects and embodiments will become apparent by reference to the drawings and by study of the following descriptions.

Exemplary embodiments are illustrated in referenced figures of the drawings. It is intended that the embodiments and figures disclosed herein are to be considered illustrative rather than limiting.

FIG. 1 is a schematic diagram illustrating an nvSRAM memory cell in accordance with one embodiment of the present invention;

FIG. 2 is a schematic diagram illustrating an nvSRAM memory cell of FIG. 1 with an attached controller;

FIG. 3 is a schematic diagram illustrating a RECALL function for an nvSRAM cell of FIG. 1;

FIG. 4 is a schematic diagram illustrating a modified RECALL function to reset the nvSRAM cell of FIG. 1;

FIG. 5 is a block diagram of an array of memory cells having a number of rows and columns including an array reset circuit coupled to the bit line pairs of memory cells in each column; and

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• Utility Patent

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