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Method and apparatus for using full-chip thermal analysis of semiconductor chip designs to compute thermal conductance

Method and apparatus for using full-chip thermal analysis of semiconductor chip designs to compute thermal conductance description/claims

This application is a continuation of U.S. patent application Ser. No. 11/198,470, filed Aug. 5, 2005. Ser. No. 11/198,470 is in turn a continuation-in-part of U.S. patent application Ser. No. 10/979,957, filed Nov. 3, 2004, and additionally claims the benefit of U.S. Provisional Patent Application Ser. No. 60/598,987, filed Aug. 5, 2004. All of these applications are herein incorporated by reference in their entireties.

The present invention generally relates to semiconductor chip design, and more particularly relates to the thermal analysis of semiconductor chip designs.

Semiconductor chips typically comprise the bulk of the components in an electronic system. These semiconductor chips are also often the hottest part of the electronic system, and failure of the system can often be traced back to thermal overload on the chips. As such, accurate estimation of a semiconductor chip design's thermal conductance is a critical parameter of semiconductor chip design.

FIG. 1 is a schematic diagram illustrating an exemplary semiconductor chip 100. As illustrated, the semiconductor chip 100 comprises one or more semiconductor devices 102a-102n (hereinafter collectively referred to as “semiconductor devices 102”), such as transistors, resistors, capacitors, diodes and the like deposited upon a substrate 104 and coupled via a plurality of wires or interconnects 106a-106n (hereinafter collectively referred to as “interconnects 106”). These semiconductor devices 102 and interconnects 106 share power, thereby distributing a thermal gradient over the chip 100 that may range from 100 to 180 degrees Celsius in various regions of the chip 100. Moreover, the thermal conductivity over the chip 100 varies with the different materials (e.g., metal, dielectric, etc.) contained therein.

Many methods currently exist for performing thermal analysis of semiconductor chips designs, e.g., to ensure that a chip constructed in accordance with a given design will not overheat and trigger a failure when deployed within an intended system. Such conventional methods, however, typically fail to provide a complete or an entirely accurate picture of the chip's operating thermal gradient. For example, typical thermal analysis models attempt to solve the temperature on the chip substrate, but do not solve the temperature in a full three dimensions, e.g., using industry standards design, package and heat sink data. Moreover, most typical methods do not account for the sharing of power among semiconductor devices and interconnects, which distributes the heat field within the chip, as discussed above.

In addition, most conventional methods for modeling heat conducting paths within semiconductor chip designs are quite complex, as extraction of conductance values involves computation of the different shapes and materials within the semiconductor chip design. The practicality of such methods is thus impacted not only by the accuracy of the thermal data provided thereto, but also by the computational inefficiency.

Therefore, there is a need in the art for a method and apparatus for using full-chip thermal analysis of semiconductor chip designs to compute thermal conductance.

A method and apparatus for using full-chip thermal analysis of semiconductor chip designs to compute thermal conductance is disclosed. One embodiment of a novel method for analyzing the conductance of a semiconductor chip design comprises receiving full-chip temperature data for the semiconductor chip design and defining at least one thermal layer within the semiconductor chip design in accordance with the full-chip temperature data. The thermal layer(s) represents variances in thermal conductance over the semiconductor chip design and does not necessarily correspond to the physical layers of the semiconductor chip design. Thus, the thermal conductances within the semiconductor chip design can be computed from the thermal layers.

So that the manner in which the above recited embodiments of the invention are attained and can be understood in detail, a more particular description of the invention, briefly summarized above, may be had by reference to the embodiments thereof which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only typical embodiments of this invention and are therefore not to be considered limiting of its scope, for the invention may admit to other equally effective embodiments.

FIG. 1 is a schematic diagram illustrating an exemplary semiconductor chip;

FIG. 2 is a schematic diagram illustrating one implementation of a thermal analysis tool according to the present invention;

FIG. 3 is a flow diagram illustrating one embodiment of a method for performing three-dimensional thermal analysis of a semiconductor chip design according to the present invention;

FIG. 4 is a graph illustrating the change in value of transistor resistance for an exemplary negative channel metal oxide semiconductor as a function of the output transition voltage;

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