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Method and apparatus for test connectivity, communication, and controlRelated Patent Categories: Error Detection/correction And Fault Detection/recovery, Pulse Or Data Error Handling, Digital Logic Testing, Scan Path Testing (e.g., Level Sensitive Scan Design (lssd))Method and apparatus for test connectivity, communication, and control description/claimsThe Patent Description & Claims data below is from USPTO Patent Application 20070089003, Method and apparatus for test connectivity, communication, and control. Brief Patent Description - Full Patent Description - Patent Application Claims
[0001] This application is a divisional of application Ser. No. 10/114,193, filed Apr. 2, 2002, currently pending; [0002] Which was a divisional of application Ser. No. 09/248,504, filed Feb. 10, 1999, U.S. Pat. No. 6,378,093, issued Apr. 23, 2002; [0003] Which claimed priority to provisional application Ser. No. 60/074,264, filed Feb. 10, 1998. BACKGROUND OF THE INVENTION [0004] 1. Field of the Invention [0005] This invention relates generally to testing of integrated circuits with scan paths and particularly relates to testing integrated circuits with parallel scan distributors and collectors controlled by a controller that includes a state machine. [0006] 2. Description of the Related Art [0007] Cost effective testing of today's complex integrated circuits is extremely important to semiconductor manufacturers from a profit and loss standpoint. The increases in complexity of state-of-the-art integrated circuits is being accompanied by an ever increasing difficulty to test the integrated circuits. New test techniques must be developed to offset this increasing integrated circuit test cost, otherwise further advancements in future integrated circuit technology may be blocked. One emerging technology that is going to accelerate the complexity of integrated circuits even more is intellectual property cores. These cores will provide highly complex pre-designed circuit functions such as; DSPs, CPUs, I/O peripherals, memories, and mixed signal A/D and D/A functions. These cores will exist in a library and can be selected and placed in an integrated circuit quickly to provide a complex circuit function. The low cost testing of integrated circuits that contain highly complex core functions will be a significant challenge. SUMMARY OF THE INVENTION [0008] The disclosed circuits provide a description of a controller for use with the parallel scan distributor and collector circuits. The controller has a test control register, a test control state machine and a multiplexer. The controller also has inputs and outputs for connection to additional controllers in a hierarchical or parallel arrangement. The controller is also programmable to provide different types of test control for testing different types of circuits. [0009] The disclosed parallel scan distributor and collector circuits provide a low power method of scan testing combinational logic within an IC by allowing scan test communication to occur over a larger number of shorter length scan paths. [0010] With a synchronizer and delay circuit, the disclosed test circuits can further reduce the power needed to test the integrated circuits. The test circuits disclosed can be used to test functional combinatorial logic, random access memory, and digital to analog and analog to digital circuitry. Conventional IEEE 1149.1 test access port or TAP circuits can be modified to operate with the disclosed scan distributor and collectors circuits and controllers. BRIEF DESCRIPTION OF THE VIEWS OF THE DRAWINGS [0011] FIG. 1 depicts an integrated circuit. [0012] FIG. 2 is a block diagram of a known parallel scan path test arrangement. [0013] FIG. 3 is a block diagram of a parallel scan path test arrangement according to the present invention. [0014] FIG. 4 is a block diagram of the scan path test arrangement of FIG. 3 further including a test controller according to the present invention. [0015] FIG. 5 is a flow chart illustrating operation of the test controller and scan path arrangement of FIG. 4. [0016] FIG. 6 is a flow chart illustrating an alternate operation of the test controller and scan path arrangement. [0017] FIG. 7 depicts an integrated circuit that includes an embedded core. [0018] FIG. 8 is a block diagram of a scan test circuit and controller arrangement for testing the integrated circuit and core of FIG. 7 according to the present invention. [0019] FIG. 9 depicts an integrated circuit including an embedded core, in which the embedded core itself includes an embedded core. [0020] FIG. 10 is a block diagram of a scan test circuit and controller arrangement for testing the integrated circuit and embedded cores of FIG. 9 according to the present invention. [0021] FIG. 11 is a block diagram of a hierarchical connection between scan test circuit arrangements according to the present invention. Continue reading about Method and apparatus for test connectivity, communication, and control... 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