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  Method and apparatus for reliable pulse event detectionUSPTO Application #: 20060076983Title: Method and apparatus for reliable pulse event detection Abstract: A circuit for detecting asynchronous events includes a first event detection latch; and a second event detection latch coupled to the first event detection latch, wherein the first event detection latch is ready to detect an event when the second event detection latch is being reset and wherein the second event detection latch is ready to detect a next event when the first event detection latch is being reset. (end of abstract) Agent: Christie, Parker & Hale, LLP - Pasadena, CA, US Inventor: Wenkwei Lou USPTO Applicaton #: 20060076983 - Class: 327020000 (USPTO) The Patent Description & Claims data below is from USPTO Patent Application 20060076983. Brief Patent Description - Full Patent Description - Patent Application Claims
CROSS-REFERENCE TO RELATED APPLICATION [0001] This Patent Application claims the benefit of the filing date of U.S. Provisional Patent Application Ser. No. 60/618,521, filed on Oct. 13, 2004 and entitled "METHOD AND APPARATUS FOR RELIABLE PULSE EVENT DETECTION," the entire content of which is hereby expressly incorporated by reference. FIELD OF THE INVENTION [0002] The present invention relates generally to electronic circuits; and more particularly to pulse event detection method and circuit. BACKGROUND OF THE INVENTION [0003] Pulse event detection is common among electronic systems. It can be performed by synchronous or asynchronous methods depending on the requirement of the system. The asynchronous method detects pulses, without the use of a clock and is suited for low power operations of a mouse button or keyboard events, for example. However, in the operation of a typical asynchronous event detection, shown in FIG. 1, the event pulse might be missed depending on the frequency of the events. [0004] For example, when a rising edge event is latched in latch 10, it triggers an interrupt 13 to a processor. After, being interrupted, the processor typically clears the event latched in latch 10 by writing to a memory location. The write operation to the memory by the processor generates a low going pulse at 12 and asynchronously clears the latch 10. The problem arises when there is an incoming rising edge next event during this interrupt-driven clear cycle. [0005] For example, after the pulse event is acknowledged and processed by a control unit of the system (e.g., a processor), the detection circuit has to be cleared and re-armed for detection of next event. It is likely that the clearing of the detection circuit masks a new incoming edge event. This causes the new incoming event to be missed and lost. [0006] Therefore, there is a need for an circuit and method for a more reliable pulse event detection. SUMMARY OF THE INVENTION [0007] The present invention is related to a solution to the above problem by employing a redundancy edge and/or level detection circuit including an edge and a level pulse detection logic, or another edge detection circuit. The present invention solves the above problem by a new design including a(n) edge/level detection latch, which begins detection after the rising edge of the "clear" pulse. In this case, the processor can check the interrupt right after the "clear" signal to make sure no edge occurs. [0008] In one embodiment, the invention is a circuit for detecting asynchronous events. The circuit includes a first event detection latch; and a second event detection latch coupled to the first event detection latch, wherein the first event detection latch is ready to detect an event when the second event detection latch is being reset and wherein the second event detection latch is ready to detect a next event when the first event detection latch is being reset. [0009] In one embodiment, the invention is a method for detecting asynchronous events. The method includes detecting a first event by a first event detection circuit; resetting the first event detection circuit after the first event is detected; detecting a second event by a second event detection circuit; and resetting the second event detection circuit after the second event is detected, wherein the first event detection circuit is ready to detect an event when the second event detection circuit is being reset and wherein the second event detection circuit is ready to detect a next event when the first event detection circuit is being reset. [0010] In one embodiment, the invention is a programmable circuit for detecting event signal. The circuit includes a first programmable event detection circuit for detecting one of the group consisting a rising edge event, a falling edge event, a high level event, and a low level event; and a second programmable event detection circuit coupled to the first programmable event detection latch for detecting one of the group consisting a rising edge event, a falling edge event, a high level event, and a low level event, wherein the first and second programmable event detection circuits operate in a ping-pong manner for detecting events. BRIEF DESCRIPTION OF THE DRAWINGS [0011] FIG. 1 shows a typical asynchronous event detection circuit; [0012] FIG. 2 is an exemplary circuit diagram for a reliable pulse event detection method and apparatus, according to one embodiment of the invention; [0013] FIG. 3 is an exemplary timing diagram for circuit of FIG. 2; [0014] FIG. 4 depicts an exemplary block diagram for a pulse event detection capable of detecting a rising edge event and/or a falling edge event, according to one embodiment of the present invention; and [0015] FIG. 5 is an exemplary circuit diagram for a pulse event detection capable of detecting a rising edge event and/or a falling edge event, according to one embodiment of the present invention. DETAILED DESCRIPTION [0016] In one embodiment, the present invention is directed to a method and apparatus for a reliable pulse event detection. FIG. 2 is an exemplary circuit diagram for a reliable pulse event detection method and apparatus, according to one embodiment of the invention. As shown, latch 101 detects the rising edge of the event 100 by latching a "high" 110 at its output 102. Multiplexer 104, controlled by the sel_level signal 107 (from the processor), selects the latched high output 102 to generate an interrupt signal 109. Once interrupted, the processor attempts to clear (re-arm) latch 101 for detection of the next event. This is performed by sending a clr103 signal 103 used to clear latch 101. At the same time, the processor toggles the sel_level signal 107, used to control the multiplexor 104. [0017] However, while latch 101 is being cleared by the clr103, the next event 100a may occur, as shown by the exemplary timing diagram of FIG. 3. This next event will be missed by latch 101, because clr103 pulse 103 is still high, as shown in FIG. 3. Nevertheless, next event 10a is captured by the level detection latch 105 by clocking a high (i.e., 111) to its output 108, as shown in the timing diagram of FIG. 3. Since the processor is still performing the interrupt routine, the write operation, and/or generating the clr103 signal, it toggles the sel_level signal 107 from an "edge detect" mode to a "level detect" mode, as shown in the timing diagram of FIG. 3. As a result, the multiplexor 104 selects the high output 108 of the latch 105, as a second interrupt 109 to the processor, as the detection of the second event 10a. This way, the level detection latch 105 begins detection right after the rising edge of the clr103 pulse 103 and processor can check the interrupt 109 right after clr103 to make sure no event edge occurs. [0018] Although, in the exemplary circuit of FIG. 2, latch 105 is depicted as a level detector, those skilled in the art will understand that latch 105 can be an edge detector similar to latch 101. Likewise, latch 101 may be a level detector similar to latch 105, depending on the application. In one embodiment, the two edge/level detector latches 101 and 105 operate in a "ping-pong" manner, in which while latch 101 is being reset (by the processor), latch 105 is ready for operation, and when latch 105 is being reset, latch 101 is ready for operation. In other words, in this manner, the two latched alternate to detect the next coming events. Continue reading... Full patent description for Method and apparatus for reliable pulse event detection Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Method and apparatus for reliable pulse event detection patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. 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