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  Method and apparatus for processing the peripheral and edge portions of a wafer after performance of a surface treatment thereonUSPTO Application #: 20080032043Title: Method and apparatus for processing the peripheral and edge portions of a wafer after performance of a surface treatment thereon Abstract: A surface processing method includes supporting a wafer in a vacuum chamber and generating a plasma in a confined portion of the chamber over only a selected portion of the wafer to thereby perform a surface processing treatment (e.g., an ashing process) on the selected portion of the wafer. While the plasma is being generated, the wafer and the confined portion of the chamber are displaced with respect to one another to thereby perform the surface processing treatment on a second selected portion of the wafer. (end of abstract)
Agent: Mayer & Williams PC - Westfield, NJ, US Inventor: Koji Miyata USPTO Applicaton #: 20080032043 - Class: 427240 (USPTO) The Patent Description & Claims data below is from USPTO Patent Application 20080032043. Brief Patent Description - Full Patent Description - Patent Application Claims
FIELD OF THE INVENTION [0001]The present invention relates generally to a method and apparatus for performing a surface treatment process, and more particularly to a method and apparatus for performing a plasma ashing process to remove a resist material or the like from a semiconductor wafer. BACKGROUND OF THE INVENTION [0002]The manufacture of integrated circuits (ICs) in a semiconductor device involves the formation of a sequence of layers that contain metal wiring. Metal interconnects and vias which form horizontal and vertical connections in the device are separated by insulating layers or inter-level dielectric layers (ILDs) to prevent crosstalk between the metal wiring that can degrade device performance. A popular method of forming an interconnect structure is a dual damascene process in which vias and trenches are filled with metal in the same step to create multi-level, high density metal interconnections needed for advanced high performance integrated circuits. The most frequently used approach is a via first process in which a via is formed in a dielectric layer and then a trench is formed above the via. Recent achievements in dual damascene processing include lowering the resistivity of the metal interconnect by switching from aluminum to copper, decreasing the size of the vias and trenches with improved lithographic materials and processes to improve speed and performance, and reducing the dielectric constant (k) of insulators or ILDs by using so-called low-k materials to avoid capacitance coupling between the metal interconnects. The expression "low-k" material has evolved to characterize materials with a dielectric constant less than about 3.9. One class of low-k material that have been explored are organic low-k materials, typically having a dielectric constant of about 2.0 to about 3.8, which may offer promise for use as an ILD. [0003]During a dual damascene process, there are typically four etches: via, trench, photoresist and polymer strip, and bottom barrier removal. Each has challenges irrespective of damascene strategy. For example, during the via etch, selectivity of the resist, selectivity of the bottom barrier and profile in the bottom of the via are critical. During the trench etch it is important to maintain the integrity of the bottom barrier without impacting the desired lateral dimensions of the trench. With regard to photoresist and polymer removal, the process of removing the photoresist mask, polymers and post etch residues after the features have been etched into the substrate is generally known as stripping or ashing. The stripping or ashing process should exhibit high selectivity since small deviations in the etched profiles can adversely impact device performance, yield and reliability of the final integrated circuit. Since many of the low-k dielectrics contain carbon within their structure, current processes exhibit reduced selectivity. Moreover, the current processes for ashing or stripping photoresist from new low-k ILD materials can cause damage to the material. For example, ashing can result in pullback of the dielectric film and/or cause an increase in the effective k value of the dielectric film. [0004]In a conventional ashing process, an oxygen-containing gas is introduced into the chamber, and the RF electric power is applied to the chamber or the like to activate the gas so that it is transformed into a plasma. The gas may be an almost pure oxygen gas, an ozone gas, a mixture thereof, or a mixture of either or both of these gases with a gas such as N.sub.2, H.sub.2 and/or NH.sub.3. [0005]To reduce damage to the low-k ILD materials caused by the ashing process, the gas pressures are often kept at a relatively low levels. Unfortunately, these ashing processes are often less effective than processes performed at higher gas pressures. As a result, ashed material may be re-deposited along the top and bottom periphery of the wafer as well as along the wafer edges. The re-deposited material can become a source of particle flaking that can adversely impact the overall IC manufacturing process. [0006]Accordingly, it would be desirable to provide a method and apparatus for removing such re-deposited ashed materials that accumulate on a semiconductor wafer. SUMMARY OF THE INVENTION [0007]In accordance with the present invention, a surface processing method is provided. The method includes supporting a wafer in a vacuum chamber and generating a plasma in a confined portion of the chamber over only a selected portion of the wafer to thereby perform a surface processing treatment on the selected portion of the wafer. While the plasma is being generated, the wafer and the confined portion of the chamber are displaced with respect to one another to thereby perform the surface processing treatment on a second selected portion of the wafer. [0008]In accordance with one aspect of the invention, the displacement is performed by rotating the wafer on a sample holder about a central axis of the wafer while the plasma remains in a fixed location in the confined portion of the chamber. [0009]In accordance with another aspect of the invention, the displacement includes repositioning the wafer to expose an edge of the wafer to the plasma. [0010]In accordance with another aspect of the invention, the first and second selected portions of the wafer define a substantially complete periphery of the wafer. [0011]In accordance with another aspect of the invention, the complete periphery of the wafer includes a top and bottom periphery of the wafer. [0012]In accordance with another aspect of the invention, the first and second selected portions of the wafer include an edge of the wafer. [0013]In accordance with another aspect of the invention, an exhaust gas is supplied over the wafer to prevent contaminated processing gases from flowing over portions of the wafer other than the first and second selected portions. [0014]In accordance with another aspect of the invention, the surface processing treatment is an ashing process. [0015]In accordance with another aspect of the invention, the surface processing treatment is an etching process. [0016]In accordance with another aspect of the invention, the surface processing treatment is a film deposition process. [0017]In accordance with another aspect of the invention, prior to generating the plasma over the selected portion of the wafer, an initial ashing process is performed on substantially an entire surface of the wafer. [0018]In accordance with another aspect of the invention, the initial ashing process is a plasma etching process. [0019]In accordance with another aspect of the invention, the surface processing treatment is performed to remove a resist mask previously formed on the wafer. [0020]In accordance with another aspect of the invention, the surface processing treatment is part of a process to form a dual damascene structure. [0021]In accordance with another aspect of the invention, a surface processing apparatus is provided that includes a vacuum chamber for processing semiconductor materials and a rotatable support for supporting a wafer within the vacuum chamber so that the wafer is selectively rotatable. A plasma discharge device is provided for generating a plasma in a confined portion of the chamber over only a peripheral and edge portion of the wafer to thereby perform a surface processing treatment on the peripheral portion of the wafer while the wafer is being rotated by the rotatable support. Continue reading... Full patent description for Method and apparatus for processing the peripheral and edge portions of a wafer after performance of a surface treatment thereon Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Method and apparatus for processing the peripheral and edge portions of a wafer after performance of a surface treatment thereon patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. 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