| Method and apparatus for plasma processing -> Monitor Keywords |
|
|
  Method and apparatus for plasma processingUSPTO Application #: 20070232085Title: Method and apparatus for plasma processing Abstract: The invention provides a plasma processing apparatus capable of minimizing the non-uniformity of potential distribution around wafer circumference, and providing a uniform process across the wafer surface. The apparatus is equipped with a focus ring formed of a dielectric, a conductor or a semiconductor and having RF applied thereto, the design of which is optimized for processing based on a design technique clarifying physical conditions for flattening a sheath-plasma interface above a wafer and the sheath-plasma interface above the focus ring. A surface voltage of the focus ring is determined to be not less than a minimum voltage for preventing reaction products caused by wafer processing from depositing thereon. The surface height, surface voltage, material and structure of the focus ring are optimized so that the height of an ion sheath formed on the focus ring surface is either equal or has a height difference within an appropriate tolerance range to the height of the ion sheath formed on the wafer surface. Optimization of the structure is realized by setting up an appropriate tolerance range taking into consideration the variation caused by consumption of the focus ring. (end of abstract) Agent: Antonelli, Terry, Stout & Kraus, LLP - Arlington, VA, US Inventors: Ryoji Nishio, Tadamitsu Kanekiyo, Yoshiyuki Oota, Tsuyoshi Matsumoto USPTO Applicaton #: 20070232085 - Class: 438798000 (USPTO) Related Patent Categories: Semiconductor Device Manufacturing: Process, Radiation Or Energy Treatment Modifying Properties Of Semiconductor Region Of Substrate (e.g., Thermal, Corpuscular, Electromagnetic, Etc.), Ionized Irradiation (e.g., Corpuscular Or Plasma Treatment, Etc.) The Patent Description & Claims data below is from USPTO Patent Application 20070232085. Brief Patent Description - Full Patent Description - Patent Application Claims
CROSS-REFERENCE TO RELATED APPLICATION [0001] This application is a Divisional application of application Ser. No. 10/902,032, filed Jul. 30, 2004, which claims priority from Japanese patent application No. JP 2004-118513, filed on Apr. 14, 2004, the contents of which are incorporated herein by reference in their entirety. FIELD OF THE INVENTION [0002] The present invention relates to the art of semiconductor fabrication. Especially, the invention relates to a structure of a wafer stage that affects the etching contour when providing an etching process to a semiconductor wafer using plasma. DESCRIPTION OF THE RELATED ART [0003] Recently, along with the enhancement in the integration of semiconductor elements, the circuit patterns have become more and more refined, and the demanded accuracy of processing dimension has become stricter. Further, the wafer diameter is increased to 300 mm in the attempt to reduce fabrication costs of the semiconductor elements, but processing is required to be uniform across the whole surface of the wafer from the center to the outer circumference thereof. However, a ceramic cover for protecting an electrostatic chuck is disposed near the outer circumference of the wafer, for example, which causes non-uniformity of the electric field at the circumference compared to the center of the wafer, and causes the drawback of non-uniformity of the wafer process. If electric field non-uniformity is caused near the outer circumference of the wafer, the ions being incident on the wafer will not be perpendicular to the wafer, by which the perpendicularity of the contour is deteriorated and the yield factor reduced. Similarly, focusing and divergence of the ions occur, by which the processing performance such as the etching rate varies greatly near the wafer edge. These are serious problems since they cause the increase of fabrication costs [0004] In order to solve this problem, many measures have been proposed for preventing the distortion of electric field of the electrode on which the wafer is placed. The structure for realizing this is called a focus ring or an edge ring, and in this specification it is referred to as a focus ring. For example, a dry etching device equipped with a ring type auxiliary plate having an adjustable height for surrounding the periphery of the wafer is proposed (refer for example to patent document 1). Further, a means for controlling an RF power (voltage or electric field) applied to the wafer edge and the outer periphery thereof by controlling the impedance of the wafer edge and the outer periphery thereof is proposed (refer for example to patent document 2). Similarly, structures for controlling the electric field near the wafer edge with a focus ring having RF applied thereto are proposed, wherein the focus ring is a conductive member (refer for example to patent document 3) or wherein the focus ring is a dielectric (refer for example to patent document 4). Further, there is a proposal of an elevated focus ring (edge ring) formed of a dielectric material or a semiconductor material for flattening the sheath-plasma interface above the wafer and the sheath-plasma interface above the focus ring when RF is not applied, and a focus ring (edge ring) having the same height as the wafer formed of dielectric or semiconductor material for flattening the sheath-plasma interface above the wafer and the sheath-plasma interface above the focus ring when RF is applied thereto (refer for example to patent document 5). Moreover, there is a proposal of a focus ring formed by assembling a dielectric and a conductor for generating a uniform sheath voltage by making the impedance between the lower electrode and plasma equal at both the wafer and the focus ring (refer for example to patent document 6) Moreover, a method for achieving a uniform process is proposed, that adjusts the intensity of RF passing the focus ring by adjusting the impedance thereof (refer for example to patent document 7). Moreover, another method for achieving a uniform process through use of a focus ring having the same height as the wafer surface is proposed (refer for example to patent document 8). [0005] Patent Document 1: [0006] Japanese Patent Application Laid-Open No. 63-229719 [0007] Patent Document 2: [0008] Japanese Patent Application Laid-Open No. 6-120140 [0009] Patent Document 3: [0010] Japanese Patent Application Laid-Open No. 5-335283 [0011] Patent Document 4: [0012] Japanese Patent Application Laid-Open No. 6-168911 [0013] Patent Document 5: [0014] International Publication under PCT No. WO 01/01445 A1 (Published in Japan as P2003-503841) [0015] Patent Document 6: [0016] International Publication under PCT No. WO 01/50497 A1 (Published in Japan as P2003-519907) [0017] Patent Document 7: [0018] Japanese Patent Application Laid-Open No. 2002-198355 [0019] Patent Document 8: [0020] Japanese Patent Application Laid-Open No. 2003-229408 [0021] Patent Document 9: [0022] Japanese Patent Application Laid-Open No. 2002-203835 [0023] According to the above-mentioned prior art methods, however, there is no disclosure of a technique for optimizing the focus ring structure. Even if the focus ring structure is determined through experiments, the design of the focus ring must be reconsidered each time the etching process is changed. In a general fabrication process, a single apparatus is not only used to carry out a single discharge process, but used to carry out multiple discharge conditions. Therefore, the focus ring must be exchanged depending on discharge conditions. In an alternative technique, a single focus ring structure can be designed to correspond to various discharge conditions by setting up a tolerance and optimizing the structure corresponding to the set tolerance. However, the prior art lacks to disclose such technique. [0024] Furthermore, since the focus ring is subjected to the application of RF voltage while being exposed to reactive plasma, the ring is consumed both physically by ions (through sputtering etc.) and chemically by reaction, by which the dimension of the ring is changed. Therefore, the electric field correcting function of the focus ring changes with time and deteriorated. Therefore, it is necessary to set up a tolerance and to optimize the structure accordingly, but the prior art lacks to disclose such technique. [0025] On the other hand, reaction products generated through wafer processing and reaction products in the gas may be deposited on the surface of the focus ring, depending on the property of the wafer processing. The deposits on the focus ring surface may become particles that adhere to the wafer and cause defective products to be fabricated. Further, during the course of the procedure starting from the state in which there are no deposits to the state in which sufficient deposition is formed, the gas-phase components released from the focus ring surface are varied, according to which the plasma status is changed. This may cause time variation of the wafer process according to which the result of wafer processing is changed with time from the starting of wafer processing. The conventional methods lack to provide a method for coping with the deposition, so the focus ring may be helpful to uniformize the processing, but it is not actually useful if deposition occurs. [0026] As disclosed in patent document 5 mentioned above, in order to uniformize the process at the wafer edge portion, it is important that the plasma-sheath interface above the wafer and the plasma-sheath interface above the focus ring are flat. However, the ion trajectory toward the wafer does not depend only on the plasma-sheath interface, but also on the flatness of the potential field within the sheath. The latter important factor has not been considered in the conventional attempt to optimize the structure. Of course, patent document 5 lacks to disclose any teachings related to determining the tolerance and optimizing the structure based thereon. The drawback of the conventional optimization process disclosed in document 5 is that there is no teaching of a physical method or design technique for flattening the plasma-sheath interface above the wafer and the plasma-sheath interface above the focus ring. The optimization of the structure is impossible to carry out without a physical mechanism or a design technique. Even when an appropriate structure is discovered through experimental methods, it is difficult to prove experimentally that the plasma-sheath interface above the wafer and the plasma-sheath interface above the focus ring are flat, and the flatness cannot be ensured. [0027] The drawback of the technique disclosed in patent document 6 mentioned above is that the generation of a uniform sheath voltage realized by equalizing the impedance between the lower electrode and plasma at the wafer portion and at the focus ring portion does not guarantee the flattening of the plasma-sheath interface above the wafer and the plasma-sheath interface above the focus ring. An additional condition must be fulfilled to ensure that the plasma-sheath interface above the wafer and the plasma-sheath interface above the focus ring are flat, but patent document 6 lacks to teach such condition. [0028] A more detailed description of these drawbacks will appear in the description of the preferred embodiment of the present invention. [0029] Considering the above drawbacks of the prior art, the first object of the present invention is to provide a wafer processing method and an etching apparatus comprising a wafer stage capable of providing uniform processing across the whole wafer plane, while minimizing the non-uniformity of the potential distribution around the wafer circumference. [0030] The second object of the present invention is to provide a wafer processing method and an etching apparatus comprising a wafer stage, wherein a tolerance of the wafer stage has been set up and the structure of the wafer stage is optimized to correspond to the set tolerance, in order to provide uniform processing across the wafer plane. Continue reading... Full patent description for Method and apparatus for plasma processing Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Method and apparatus for plasma processing patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. Start now! - Receive info on patent apps like Method and apparatus for plasma processing or other areas of interest. ### Previous Patent Application: Manufacturing method for semiconductor device Next Patent Application: Signal processing device and control unit Industry Class: Semiconductor device manufacturing: process ### FreshPatents.com Support Thank you for viewing the Method and apparatus for plasma processing patent info. IP-related news and info Results in 4.50795 seconds Other interesting Feshpatents.com categories: Daimler Chrysler , DirecTV , Exxonmobil Chemical Company , Goodyear , Intel , Kyocera Wireless , |
||
