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  Method and apparatus for performing testing of interconnectionsUSPTO Application #: 20060167646Title: Method and apparatus for performing testing of interconnections Abstract: The present invention provides a method and apparatus configured to allow testing of interconnections between components in a system. The present invention utilizes a source of a known pattern, for example a pattern buffer, in a first component of the system and a capture buffer located in a second component of the system. (end of abstract) Agent: Morgan Lewis & Bockius LLP/rambus Inc. - Palo Alto, CA, US Inventor: Philip Yeung USPTO Applicaton #: 20060167646 - Class: 702120000 (USPTO) Related Patent Categories: Data Processing: Measuring, Calibrating, Or Testing, Testing System, Of Circuit, Including Input/output Or Test Mode Selection Means The Patent Description & Claims data below is from USPTO Patent Application 20060167646. Brief Patent Description - Full Patent Description - Patent Application Claims
CROSS REFERENCE TO RELATED APPLICATION [0001] This application is a continuation of U.S. patent application Ser. No. 10/663,572, filed Sep. 15, 2003, entitled "Method and Apparatus for Performing Testing of Interconnections," which application is incorporated by reference herein in its entirety. BACKGROUND OF THE INVENTION [0002] 1. Field of the Invention [0003] The invention relates to the testing of electronic equipment. [0004] 2. Description of the Related Art [0005] In the manufacturing of electronic equipment, it is beneficial to test the proper operation of the manufactured equipment in order to maintain an expected level of quality. Testing may be performed on individual electronic components, subsystems, and complete systems. Since testing of subsystems and systems involves testing of interconnections between components, techniques have been developed to facilitate such testing. [0006] One example of a technique for testing of interconnections between components is referred to as boundary scan. Boundary scan involves providing registers and supporting circuitry in components in accordance with an established boundary scan standard, such as Institute of Electrical and Electronics Engineers, Inc. (IEEE) Standard 1149.1, which was developed based on a proposal by the Joint Test Action Group (JTAG). A component with provisions for boundary scan may be configured using a test access port (TAP) to output or receive as input digital signals on the input/output (I/O) pins of the component. The TAP includes five pins consisting of the following: a test data input (TDI), a test data output (TDO), a test mode select (TMS), a test clock (TCK), and a test reset (TRST). Testing of an interconnection between two components is accomplished by configuring a first component to output a signal of a specified logic level and configuring a second component to receive as an input that signal and to identify the received logic level of that signal. An external test controller compares the logic level of the output signal with the received logic level of the input signal to determine if the interconnection between the components is passing the signal properly. The registers provided for boundary scan are configured to operate as shift registers, allowing the data of the output signal and the input signal to be shifted through the boundary scan chain, both within a component and among several components. [0007] However, as the data rates with which components communicate increase, the ability to provide for boundary scan testing becomes increasingly difficult. Yet, such increased data rates require even higher standards of performance from the interconnections for which such testing is frustrated. Without an effective testing technique, assembly yield would be decreased, and total manufacturing cost would be increased. Also, some IC devices, such as memory devices, often don't support the additional pins due to package and silicon cost and complexity associated with the boundary scan macro. Thus, a technique is needed to provide a capability of advanced testing in modern electronic equipment. BRIEF DESCRIPTION OF THE DRAWINGS [0008] The present invention may be better understood, and its features made apparent to those skilled in the art by referencing the accompanying drawings. [0009] FIG. 1 is a block diagram illustrating a system configured to allow interconnect testing in accordance with an embodiment of the present invention. [0010] FIG. 2 is a block diagram illustrating a testing environment within which one or more embodiments of the present invention may be practiced. [0011] FIG. 3 is a block diagram illustrating a memory system configured to allow interconnect testing in accordance with an embodiment of the present invention. [0012] FIG. 4 is a flow diagram illustrating a method for interconnection testing in accordance with at least one embodiment of the present invention. [0013] FIG. 5 is a flow diagram illustrating a method in accordance with an embodiment of the present invention. [0014] FIG. 6 is a flow diagram illustrating a method in accordance with an embodiment of the present invention. [0015] The use of the same reference symbols in different drawings indicates similar or identical items. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT [0016] The present invention provides a method and apparatus configured to allow testing of interconnections between components in a system. The present invention utilizes a source of a known pattern, for example a pattern buffer, in a first component of the system and a capture buffer located in a second component of the system. The present invention avoids the need to introduce additional logic circuitry in line with existing input and output paths and avoids additional electrical loading of critical input and output circuitry, thereby avoiding the performance limitations that can be introduced by the introduction of such circuitry. Also, embodiments of the present invention can allow more rapid testing of systems by avoiding long chains of shift registers in series with the testing path. Also, embodiments of the present invention may be implemented to avoid the specific pin requirements mandated by the boundary scan technique, allowing the use of fewer pins and the possibility of reusing existing pins, for example, existing pins for implementing an existing communication path independent of the interconnections being tested, such as a serial link. [0017] Moreover, embodiments of the present invention may be particularly suitable for use in memory systems, both because of the performance penalties that would be incurred in memory systems by attempts to implement prior art testing techniques and by the benefits to be achieved by providing an efficient technique for testing the typically large number of interconnect conductors found in memory systems. [0018] Embodiments of the present invention are useful in that they are capable of providing "at speed" wire testing, in other words, being able to test interconnections using signals having similar alternating-current (AC) characteristics, including frequency, as signals intended to be present during normal operation of such devices. [0019] FIG. 1 is a block diagram illustrating a system configured to allow interconnect testing in accordance with an embodiment of the present invention. The system comprises a first component 101 coupled to a second component 102 via interconnection 103. First component 101 comprises a first core circuitry 104, a first interface circuitry 106, and a first communication path 105 coupling first core circuitry 104 to first interface circuitry 106. Second component 102 comprises second core circuitry 107 coupled to second interface circuitry 109 via second communication path 108. First interface circuitry 106 of first component 101 is coupled to interconnection 103 and provided communication to second component 102 via interconnection 103. Second interface circuitry 109 of second component 102 is coupled to interconnection 103 and provides communication with first component 101 via interconnection 103. [0020] In at least one embodiment, interconnection 103 comprises interconnection 122, which is configured to communication information from first component 101 to second component 102, and second interconnection 123, which is configured to communication information from second component 102 to first component 101. In at least one embodiment, first communication path 105 comprises first transmit communication path 110 and first receive communication path 111. First transmit communication path 110 may include first multiplexer 118, which is configured to select an input from among first transmit communication path 110 and input 126, which is coupled to an output of pattern buffer 119. Multiplexer 118 provides an output at node 124, which is a continuation of first transmit communication path 110. First transmit capture buffer 114 is coupled to node 124 or, in the absence of multiplexer 118, to first transmit communication path 110. First receive capture buffer 115 is coupled to first receive communication path 111. Continue reading... Full patent description for Method and apparatus for performing testing of interconnections Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Method and apparatus for performing testing of interconnections patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. Start now! - Receive info on patent apps like Method and apparatus for performing testing of interconnections or other areas of interest. ### Previous Patent Application: Apparatus and method for compensating clock period elongation during scan testing in an integrated circuit (ic) Next Patent Application: Sensing and analysis of ambient contextual signals for discriminating between indoor and outdoor locations Industry Class: Data processing: measuring, calibrating, or testing ### FreshPatents.com Support Thank you for viewing the Method and apparatus for performing testing of interconnections patent info. IP-related news and info Results in 8.92035 seconds Other interesting Feshpatents.com categories: Computers: Graphics , I/O , Processors , Dyn. Storage , Static Storage , Printers |
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