| Method and apparatus for identifying connections between configurable nodes in a configurable integrated circuit -> Monitor Keywords |
|
|
  Method and apparatus for identifying connections between configurable nodes in a configurable integrated circuitUSPTO Application #: 20070245287Title: Method and apparatus for identifying connections between configurable nodes in a configurable integrated circuit Abstract: Some embodiments provide a method that defines a set of connections that connect the nodes in a configurable node array. The method identifies different sets of connections for connecting a set of the nodes. For each identified set of connections, the method computes a metric score that quantifies a quality of the identified set of connections. The method then selects one of the identified sets of connections to connect the configurable nodes in the array. (end of abstract) Agent: Adeli Law Group, A Professional Law Corporation - Los Angeles, CA, US Inventors: Andre Rohe, Steven Teig USPTO Applicaton #: 20070245287 - Class: 716016000 (USPTO) Related Patent Categories: Data Processing: Design And Analysis Of Circuit Or Semiconductor Mask, Circuit Design, Routing (e.g., Routing Map, Netlisting), Pla, Pld, Fpga, Or Mcm The Patent Description & Claims data below is from USPTO Patent Application 20070245287. Brief Patent Description - Full Patent Description - Patent Application Claims
FIELD OF THE INVENTION [0001] The present invention is directed towards method and apparatus for identifying connections between configurable nodes in a configurable integrated circuit. BACKGROUND OF THE INVENTION [0002] The use of configurable integrated circuits ("IC's") has dramatically increased in recent years. One example of a configurable IC is a field programmable gate array ("FPGA"). An FPGA is a field programmable IC that has an internal array of logic circuits (also called logic blocks) that are connected together through numerous interconnect circuits (also called interconnects). In an FPGA, the internal array of logic and interconnect circuits is typically surrounded by input/output blocks. Like some other configurable IC's, the logic and interconnect circuits of an FPGA are configurable. [0003] FIG. 1 illustrates an array structure 100 of a prior art FPGA. As shown in this figure, the array 100 includes numerous logic circuits 105 and interconnect circuits 110. In this architecture, the logic circuit 105 are referred to configurable logic blocks (CLB's). Each CLB is formed by several configurable look-up tables (LUT's), where each LUT is a configurable logic circuit. [0004] As shown in FIG. 1, the FPGA array structure 100 has two types of interconnect circuits 110a and 110b. Interconnect circuits 110a are connection boxes that connect CLB's 105 and interconnect circuit 110b to other CLB's 105 and interconnect circuits 110b. Interconnect circuits 110b, on the other hand, are switchboxes that connect the connection boxes 110a to other connection boxes 110a. [0005] Although not explicitly illustrated in FIG. 1, a CLB 105 can connect to CLB's that are several columns or several rows away from it in the array. FIG. 2 illustrates several such connections in a prior configurable node architecture. Specifically, this figure illustrates an array 205 of CLB's 210 without showing any of the intervening switch and connection boxes. As shown in this figure, a CLB 210a connects to CLB's that are one, two, three and six rows above and below it, and to CLB's that are one, two, three, and six columns to its right and left. [0006] The advantage of the connection architecture illustrated in FIG. 2 is that it allows one CLB to connect to another CLB that is much farther away where the distance is measured in terms of connection between two CLB's. On the other hand, this architecture requires the use of multiple connections to connect two CLB's that are in two different rows and columns. This requirement makes the connection architecture illustrated in FIG. 2 inefficient and expensive as each connection requires the use of transistor switching logic. [0007] Also, the connection architecture illustrated in FIG. 2 is not designed to optimize the number of CLB's reachable from any given CLB. Specifically, this architecture employs the same connection scheme for each CLB. Hence, as shown in FIG. 3, this architecture can result in a cycle between two CLB's 305 and 310 in the same column, or two CLB's 315 and 320 in the same row. Such cycles are undesirable as they come at the expense of reachability of other CLB's. The uniform connection architecture of FIG. 2 is also inefficient as it provides more ways than necessary for reaching one CLB from another CLB. This redundancy is illustrated in FIG. 3, which illustrates that the CLB 325 can connect to CLB 330 through two different sets of connections, one that goes through CLB 335 and one that goes through CLB 340. This redundancy is undersirable as it comes at the expense of reachability of other CLB's. [0008] There is a need in the art for a configurable IC that has a wiring architecture that increases the interconnectivity between the configurable nodes. Ideally, this wiring architecture is optimized for the interconnectivity between the configurable nodes of the configurable IC. There is also a need for a method that identifies optimal connection schemes for connecting the configurable nodes of a configurable IC. SUMMARY OF THE INVENTION [0009] Some embodiments provide a method that defines a set of connections that connect the nodes in a configurable node array. The method identifies different sets of connections for connecting a set of the nodes. For each identified set of connections, the method computes a metric score that quantifies a quality of the identified set of connections. The method then selects one of the identified sets of connections to connect the configurable nodes in the array. BRIEF DESCRIPTION OF THE DRAWINGS [0010] The novel features of the invention are set forth in the appended claims. However, for purpose of explanation, several embodiments of the invention are set forth in the following figures. [0011] FIG. 1 illustrates an array structure of a prior art FPGA. [0012] FIG. 2 illustrates several direction connections in a prior configurable node architecture. [0013] FIG. 3 illustrates shortcomings of the architecture presented in FIGS. 2. [0014] FIG. 4 illustrates an example of a configurable logic circuit that can perform a set of functions. [0015] FIG. 5 illustrates an example of a configurable interconnect circuit. [0016] FIG. 6 illustrates an example of a configurable node array. [0017] FIGS. 7-10 illustrate several examples of configurable nodes in a configurable node array. [0018] FIGS. 11 and 12 illustrate examples of two direct connections with intervening buffer circuits. [0019] FIG. 13 presents topologic illustrations of several direct connections in a configurable node array of some embodiments of the invention. [0020] FIGS. 14A-14B illustrate examples of different geometric realizations for some of the direct connections topologically illustrated in FIG. 11. Continue reading... Full patent description for Method and apparatus for identifying connections between configurable nodes in a configurable integrated circuit Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Method and apparatus for identifying connections between configurable nodes in a configurable integrated circuit patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. Start now! - Receive info on patent apps like Method and apparatus for identifying connections between configurable nodes in a configurable integrated circuit or other areas of interest. ### Previous Patent Application: Memory re-implementation for field programmable gate arrays Next Patent Application: Operational cycle assignment in a configurable ic Industry Class: Data processing: design and analysis of circuit or semiconductor mask ### FreshPatents.com Support Thank you for viewing the Method and apparatus for identifying connections between configurable nodes in a configurable integrated circuit patent info. IP-related news and info Results in 0.74894 seconds Other interesting Feshpatents.com categories: Tyco , Unilever , Warner-lambert , 3m |
||
