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  Method and apparatus for flip-chip packaging providing testing capabilityUSPTO Application #: 20060240595Title: Method and apparatus for flip-chip packaging providing testing capability Abstract: A method and apparatus for increasing the integrated circuit density in a flip chip semiconductor device assembly including an interposer substrate facilitating use with various semiconductor die conductive bump arrangements. The interposer substrate includes a plurality of recesses formed in at least one of a first surface and a second surface thereof, wherein the recesses are arranged in a plurality of recess patterns. The interposer substrate also provides enhanced accessibility for test probes for electrical testing of the resulting flip chip semiconductor device assembly. (end of abstract) Agent: Trask Britt - Salt Lake City, UT, US Inventors: Teck Kheng Lee, Wuu Yean Tay, Kian Chai Lee USPTO Applicaton #: 20060240595 - Class: 438108000 (USPTO) Related Patent Categories: Semiconductor Device Manufacturing: Process, Packaging (e.g., With Mounting, Encapsulating, Etc.) Or Treatment Of Packaged Semiconductor, Assembly Of Plural Semiconductive Substrates Each Possessing Electrical Device, Flip-chip-type Assembly The Patent Description & Claims data below is from USPTO Patent Application 20060240595. Brief Patent Description - Full Patent Description - Patent Application Claims
CROSS-REFERENCE TO RELATED APPLICATIONS [0001] This application is a divisional of application Ser. No. 10/150,892, filed May 17, 2002, pending, which is related to U.S. patent application Ser. No. 09/944,465 filed Aug. 30,2001 and entitled MICROELECTRONIC DEVICES AND METHODS OF MANUFACTURE, and to the following U.S. patent applications filed on even date therewith: Ser. No. 10/150,893 (Attorney Docket No. 4812US), entitled INTERPOSER CONFIGURED TO REDUCE THE PROFILES OF SEMICONDUCTOR DEVICE ASSEMBLIES AND PACKAGES INCLUDING THE SAME AND METHODS; Ser. No. 10/150,516 (Attorney Docket No. 4878US), entitled SEMICONDUCTOR DIE PACKAGES WITH RECESSED INTERCONNECTING STRUCTURES AND METHODS FOR ASSEMBLING THE SAME; Ser. No. 10/150,653 (Attorney Docket No. 4879US), entitled FLIP CHIP PACKAGING USING RECESSED INTERPOSER TERMINALS; Ser. No. 10/150,902 (Attorney Docket No. 4973US), entitled METHOD AND APPARATUS FOR DIELECTRIC FILLING OF FLIP CHIP ON INTERPOSER ASSEMBLY; and Ser. No. 10/150,901 (Attorney Docket No. 4974US), entitled METHODS FOR ASSEMBLY AND PACKAGING OF FLIP CHIP CONFIGURED DICE WITH INTERPOSER. BACKGROUND OF THE INVENTION [0002] 1. Field of the Invention [0003] The present invention relates generally to packaging of semiconductor dice and, more specifically, to packaging of flip-chip configured semiconductor dice employing an interposer substrate having recesses in one or both sides thereof for receiving discrete conductive elements projecting from the semiconductor dice. [0004] 2. State of the Art [0005] Chip-On-Board ("COB") or Board-On-Chip ("BOC") technology is used to attach a semiconductor die directly to a carrier substrate such as a printed circuit board ("PCB"), or an interposer may be employed and attachment may be effected using flip chip attachment, wire bonding, or tape automated bonding ("TAB"). [0006] Flip chip attachment generally includes electrically and mechanically attaching a semiconductor die by its active surface to an interposer or other carrier substrate using a pattern of discrete conductive elements therebetween. The discrete conductive elements are generally disposed on the active surface of the die during fabrication thereof, but may instead be disposed on the carrier substrate. The discrete conductive elements may comprise minute conductive bumps, balls or columns of various configurations. Each discrete conductive element is placed corresponding to mutually aligned locations of bond pads (or other I/O locations) on the semiconductor die and terminals on the carrier substrate when the two components are superimposed. The semiconductor die is thus electrically and mechanically connected to the carrier substrate by, for example, reflowing conductive bumps of solder or curing conductive or conductor-filled epoxy bumps. A dielectric underfill may then be disposed between the die and the carrier substrate for environmental protection and to enhance the mechanical attachment of the die to the carrier substrate. [0007] Wire bonding and TAB attachment techniques generally begin with attaching a semiconductor die by its back side to the surface of a carrier substrate with an appropriate adhesive, such as an epoxy or silver solder. In wire bonding, a plurality of fine wires is discretely attached to bond pads on the semiconductor die and then extended and bonded to corresponding terminal pads on the carrier substrate. A dielectric encapsulant such as a silicone or epoxy may then be applied to protect the fine wires and bond sites. In TAB, ends of metal traces carried on a flexible insulating tape such as a polyimide are attached, as by thermocompression bonding, directly to the bond pads on the semiconductor die and corresponding terminal pads on the carrier substrate. [0008] Higher performance, lower cost, increased miniaturization of components, and greater packaging density of integrated circuits are ongoing goals of the computer industry. As new generations of integrated circuit products are released, the number of components used to fabricate them tends to decrease due to advances in technology even though the functionality of the products increase. For example, on the average, there is approximately a ten percent decrease in components for every product generation over the previous generation having equivalent functionality. [0009] Recent trends in packaging are moving with increasing rapidity toward flip chip attachment due to improved electrical performance and greater packaging density. However, flip chip attachment is not without problems, such as the high cost for a third metal reroute of bond pads from the middle or periphery of a die to a two-dimensional array which, in turn, may result in overlong and unequal length electrical paths. In addition, many conventional flip chip techniques exhibit a lack of consistent reliability of the interconnections between the chip and the interposer or other carrier substrate as a result of the increased miniaturization as well as difficulties in mutual alignment of the die and carrier substrate to effect such interconnections. Effective rerouting of bond pads may also be limited by die size. Another hindrance to flip chip packaging has been difficulty in electrically testing completed flip chip semiconductor device assemblies using existing test probe equipment. Thus, even if a semiconductor die in the assembly is a so-called "known good die," the assembly itself may exhibit defects which are not easily detected and which may, even if detected, be at a stage in the fabrication process subsequent to encapsulation, rendering rework of the assembly difficult if not impossible. [0010] Further, flip chip packages for a bumped semiconductor die employing an interposer may be undesirably thick due to the combined height of the die and interposer. This is due to the use in conventional packaging techniques of relatively costly interposers comprising dual conductive layers having a dielectric member sandwiched therebetween, the bumped semiconductor die resting on and connected to traces of the conductive layer on one side of the interposer and electrically connected to traces of the conductive layer on the opposing side, conductive vias extending therebetween. Finally, underfilling a flip chip-attached semiconductor die to a carrier substrate with dielectric filler material can be a lengthy and often unreliable process, and the presence of the underfill makes reworking of defective assemblies difficult if not impossible. [0011] Other difficulties with conventional packages include an inability to accommodate die size reductions, or "shrinks," as a given design progresses through several generations without developing new interposer designs and tooling. As more functionality is included in dice, necessitating a greater number of inputs and outputs (I/Os), decreased spacing or pitch between the I/Os places severe limitations on the use of conventional interposers. In addition, with conventional packages, a die is not tested until package assembly is complete, resulting in excess cost since a defective die or die and interposer assembly is not detected until the package is finished. [0012] For example, U.S. Pat. No. 5,710,071 to Beddingfield et al. discloses a fairly typical flip chip attachment of a semiconductor die to a substrate and a method of underfilling a gap between the semiconductor die and substrate. In particular, the semiconductor die is attached facedown to the substrate, wherein conductive bumps on the die are directly bonded to bond pads on the upper surface of the substrate, which provides the gap between the die and substrate. The underfill material flows through the gap between the semiconductor die and the substrate via capillary action toward an aperture in the substrate, thereby expelling air in the gap through the aperture in the substrate in an effort to minimize voids in the underfill material. However, such an underfilling method still is unnecessarily time consuming due to having to underfill the entire semiconductor die. Further, the flip chip attachment technique disclosed in U.S. Pat. No. 5,710,071 exhibits difficulties in aligning the conductive bumps with the bond pads on the substrate and requires the expense of having a third metal reroute in the substrate. [0013] Therefore, it would be advantageous to improve the reliability of interconnections between a chip and a carrier substrate such as an interposer by achieving accurate alignment of the interconnections, an improved underfill process, and the elimination of the necessity for a third metal reroute, while reducing total assembly height in combination with the ability to employ commercially available, widely practiced semiconductor device fabrication techniques and materials as well as existing test equipment. BRIEF SUMMARY OF THE INVENTION [0014] The present invention relates to methods and apparatus for assembling, testing and packaging individual and multiple semiconductor dice with an interposer substrate in a flip chip-type arrangement and, further, the present invention relates to an interposer substrate having multiple recess patterns for mounting semiconductor dice with differently spaced and sized conductive bump configurations. The present invention provides a flip chip semiconductor device assembly substantially reduced in height or thickness and with improved mechanical and electrical reliability of the interconnections between a semiconductor die and a carrier substrate in comparison to conventional flip chip assemblies, while also improving the alignment capability of attaching the semiconductor die to the interposer substrate. The present invention also eliminates the requirement of a third metal reroute necessitated in most flip chip assemblies and eliminates the need for underfilling or reduces the time for underfilling if optionally effected. In addition, the present invention facilitates relatively simple and efficient testing of the semiconductor assembly. [0015] The flip chip semiconductor device assembly of the present invention includes an interposer substrate having a first surface and a second surface, wherein at least one of the first surface and the second surface includes multiple recesses formed therein and arranged in at least two different recess patterns for attaching one or more conductively bumped semiconductor dice thereto. The one or more conductively bumped semiconductor dice may be assembled face (or active surface) down to the interposer substrate in a flip chip-type arrangement so that the conductive bumps of the semiconductor die or dice are disposed in a corresponding recess pattern. Conductive elements in the recesses are interconnected by traces to test pads that are exposed proximate a periphery on at least one of the first and second surfaces of the interposer substrate. Such test pads allow easy access for probe testing the electrical integrity of the one or more semiconductor dice mounted to the interposer substrate. [0016] In this manner, the recesses of the at least two different recess patterns are spaced, sized and configured to substantially receive the conductive bumps on the conductively bumped semiconductor die or dice to an extent so that an active surface of each semiconductor die lies immediately adjacent a surface of the interposer substrate. An adhesive element in the form of a liquid or gel adhesive or an adhesive-coated tape may optionally be disposed between the semiconductor die and adjacent interposer substrate surface. As such, there is a reduction in the height of the flip chip assembly due to the conductive bumps being substantially or even completely received in the recesses, which allows for the conductive bumps on the die to be formed larger for increased reliability without increasing the height of the flip chip assembly while also removing the need for a third metal reroute on the semiconductor die. Furthermore, such a flip chip semiconductor device assembly may eliminate the need for underfilling between a semiconductor die and the interposer substrate. If underfilling is employed, the present invention reduces the time for underfilling the assembly and amount of dielectric filler required, since any space in a recess proximate a conductive bump is minimal and vertical space, or standoff, between the semiconductor die and adjacent interposer substrate surface is at least reduced and, in some, instances greatly reduced due to the presence of the adhesive element. [0017] In a first embodiment, the interposer substrate includes multiple recesses formed in a first recess pattern on the first surface thereof and a second recess pattern on the second surface thereof. The first and second recess patterns are configured such that semiconductor dice having differently spaced and arranged conductive bump configurations thereon (including differently sized semiconductor dice) may each be mounted to the interposer substrate. In this manner, the interposer substrate of the first embodiment may facilitate mounting two semiconductor dice thereto by mounting a first die on the first surface of the interposer substrate and mounting a second die on the second surface of the interposer substrate. [0018] In a second embodiment, the interposer substrate includes multiple recesses formed in a first recess pattern and a second, different recess pattern in the first surface thereof. Such first and second recess patterns enable semiconductor dice having differently spaced and arranged conductive bump configurations thereon (including differently sized dice) to be alternatively mounted to a first surface of the interposer substrate. In this manner, the interposer substrate of the second embodiment facilitates the option of mounting differently sized dice and/or semiconductor dice having differently spaced conductive bump configurations. [0019] In a third embodiment, the interposer substrate includes multiple recesses formed in a first recess pattern and a second, different recess pattern on the first surface of the interposer substrate and a third recess pattern and a fourth, different recess pattern on the second surface of the interposer substrate. The first and second recess patterns are configured so that semiconductor dice having differently spaced and arranged conductive bump configurations thereon (including differently sized semiconductor dice) may be optionally mounted to a first surface of the interposer substrate and the third and fourth recess patterns are configured so that semiconductor dice having differently spaced and arranged conductive bump configurations thereon (including differently sized semiconductor dice) may be optionally mounted to a second surface of the interposer substrate. In this manner, the interposer substrate of the third embodiment facilitates the option of mounting differently sized dice and/or semiconductor dice having differently spaced conductive bump configurations on both the first surface and the second surface of the interposer substrate. [0020] In a fourth embodiment, the interposer substrate includes multiple recesses formed in first, second, third and fourth different recess patterns in the first surface of the interposer substrate. Such recess patterns each are configured and sized so that semiconductor dice having differently spaced conductive bump configurations thereon (including differently sized semiconductor dice) may be optionally mounted to a first surface of the interposer substrate. Thus, the interposer substrate of the fourth embodiment facilitates the option of mounting differently sized dice and/or semiconductor dice having differently spaced conductive bump configurations on the first surface of the interposer substrate. [0021] The recess patterns referred to in the interposer substrate of the previous embodiments may be staggered and/or aligned with respect to each other. Also, the recess patterns may include some recess patterns that are staggered with respect to each other and some recess patterns that are aligned with respect to each other. Continue reading... Full patent description for Method and apparatus for flip-chip packaging providing testing capability Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Method and apparatus for flip-chip packaging providing testing capability patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. 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