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  Method and apparatus for detection and prevention of bulk cmos latchupUSPTO Application #: 20080048683Title: Method and apparatus for detection and prevention of bulk cmos latchup Abstract: A method and apparatus are provided for detection and prevention of bulk complementary metal oxide semiconductor (CMOS) latchup. A separate power distribution is provided for coupling a positive voltage supply rail to the N well and a ground voltage supply rail to the P well of the CMOS circuit. At least one sensor monitors current flow in a bias voltage applied to at least one of an N well and a P well of the CMOS circuitry. A latchup event is detected responsive to a predefined increase in the monitored current flow. A switch temporarily interrupts the connection of at least one of the N well and the P well to the respective voltage supply rail when the latchup event is detected. (end of abstract) Agent: Ibm Corporation RochesterIPLaw Dept 917 - Rochester, MN, US Inventor: Delbert R. Cecchi USPTO Applicaton #: 20080048683 - Class: 324719000 (USPTO) The Patent Description & Claims data below is from USPTO Patent Application 20080048683. Brief Patent Description - Full Patent Description - Patent Application Claims
FIELD OF THE INVENTION [0001] The present invention relates generally to the field of semiconductor manufacturing, and more particularly, relates to a method and apparatus for detection and prevention of bulk complementary metal oxide semiconductor (CMOS) latchup. DESCRIPTION OF THE RELATED ART [0002] Latchup is a significant problem in complementary metal oxide semiconductor (CMOS) bulk integrated circuits. In the internal area of conventional CMOS logic chips latchup typically is not a problem because there is no source of current to trigger the latchup. However, in space applications the current can be provided by the impact of a charged particle. [0003] Conventional CMOS circuits are susceptible to latchup, for example, in space applications due to the presence of parasitic bipolar transistors in their construction. [0004] FIG. 1 illustrates a conventional latchup structure including parasitic bipolar transistors as shown for example that result when a CMOS inverter stage is formed by a P-channel field effect transistor (PFET) and an N-channel field effect transistor (NFET). The parasitic bipolar transistors normally are inactive or turned off. However, a latchup event, for example, resulting from the impact of a charged particle, the parasitic bipolar transistors are turned on conducting current. If such a latchup is not detected and interrupted, CMOS integrated circuits can be destroyed. [0005] FIGS. 2A and 2B respectively illustrate a double well and a triple well CMOS bulk integrated circuit structure. In conventional CMOS logic circuits, there are bias contacts to the N well and P well in a triple well technology. These bias voltages are normally directly connected to the VDD and GND power grids in conventional CMOS circuits. [0006] A need exists for an effective mechanism for detection and prevention of bulk complementary metal oxide semiconductor (CMOS) latchup. SUMMARY OF THE INVENTION [0007] Principal aspects of the present invention are to provide a method and apparatus for detection and prevention of bulk complementary metal oxide semiconductor (CMOS) latchup. Other important aspects of the present invention are to provide such method and apparatus for detection and prevention of bulk complementary metal oxide semiconductor (CMOS) latchup substantially without negative effect and that overcome many of the disadvantages of prior art arrangements. [0008] In brief, a method and apparatus are provided for detection and prevention of bulk complementary metal oxide semiconductor (CMOS) latchup. At least one sensor is provided to monitor current flow in a bias voltage applied to at least one of an N well and a P well of the CMOS circuitry. At least one switch is coupled between either the positive voltage supply rail and the N well or the ground voltage supply rail and the P well of the CMOS circuitry. A latchup event is detected responsive to a predefined increase in the monitored current flow. The switch temporarily interrupts the connection of at least one of the N well and the P well to the respective voltage supply rail when the latchup event is detected. BRIEF DESCRIPTION OF THE DRAWINGS [0009] The present invention together with the above and other objects and advantages may best be understood from the following detailed description of the preferred embodiments of the invention illustrated in the drawings, wherein: [0010] FIG. 1 is a schematic of a conventional latchup structure including parasitic bipolar transistors formed with a conventional CMOS inverter stage; [0011] FIGS. 2A and 2B are cross sectional views respectively illustrating a double well and a triple well bulk CMOS integrated circuit structure; [0012] FIGS. 3 and 4 schematic diagrams illustrating exemplary apparatus for detection and prevention of bulk complementary metal oxide semiconductor (CMOS) latchup in accordance with the preferred embodiment; and [0013] FIG. 5 is a cross sectional view illustrating a bulk CMOS integrated circuit structure including an exemplary sensor and separate N well bias contacts in accordance with the preferred embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS [0014] Having reference now to the drawings, in FIG. 3, there is shown exemplary apparatus for detection and prevention of bulk complementary metal oxide semiconductor (CMOS) latchup generally designated by the reference character 300 in accordance with the preferred embodiment. Latchup detection and prevention apparatus 300 is shown with conventional CMOS circuit latchup structure, such as including parasitic transistors of a CMOS inverter as shown in FIG. 1. [0015] Latchup detection and prevention apparatus 300 includes a sensor and N well bias function generally designated 302 coupled to the N well, and a sensor and P well bias function generally designated 304 coupled to the P well. The sensor and N well bias function 302 includes a sensor resistor 306 coupled to the N well and the sensor and P well bias function 304 includes a sensor resistor 308 coupled to the P well. [0016] FIG. 4 further illustrates exemplary apparatus for detection and prevention of bulk complementary metal oxide semiconductor (CMOS) latchup generally designated by the reference character 400 in accordance with the preferred embodiment. Latchup detection and prevention apparatus 400 includes a comparator 402 coupled to the sensor and N well bias function 302 and a comparator 404 coupled to the sensor and N well bias function 302. The sensor and N well bias function 302 includes the sensor resistor 306 coupled between a positive voltage supply rail VDD and a sensor contact 406 connected to the N well of CMOS circuitry 408. The sensor and P well bias function 304 includes the sensor resistor 308 coupled between a ground voltage supply rail GND and a sensor contact 410 connected to the P well of CMOS circuitry 408. [0017] In accordance with features of the invention, a separate power distribution is provided for the N well and P well. A separate power distribution grid couples a positive voltage supply rail to the N well and the CMOS circuit 408 and a ground voltage supply rail to the P well and the CMOS circuit 408. The current in the bias voltage is monitored and, for example, either limited to a level insufficient to sustain a latchup or an increase in current is detected indicating a latchup event. A switch is operated for temporarily interrupting a connection of the N well and the P well to the respective positive or ground voltage supply rail, or to interrupt the current flow responsive to a detected latchup event. This destroys the state of the protected CMOS circuit 408, but circuit operation can be restored while avoiding circuit failure from an otherwise sustained latchup event. [0018] As shown in FIG. 4, a switch 412 is connected between the positive voltage supply rail VDD to an N well contact 414 and the CMOS circuit 408. The switch 412, such as a P-channel field effect transistor (PFET), receives a control signal from the comparator 402 for temporarily interrupting a connection of the N well and CMOS circuit 408 to the voltage supply rail VDD and current is interrupted responsive to a detected latchup event. [0019] As shown in FIG. 4, a switch 416 is connected between the ground voltage supply rail GND to a P well contact 418 and the CMOS circuit 408. The switch 416, such as an N-channel field effect transistor (NFET), receives a control signal from the comparator 404 for temporarily interrupting a connection of the P well and CMOS circuit 408 to the ground voltage supply rail GND so that current is interrupted responsive to a detected latchup event. Continue reading... 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