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Method and apparatus for converting globally clock-gated circuits to locally clock-gated circuitsRelated Patent Categories: Data Processing: Design And Analysis Of Circuit Or Semiconductor Mask, Circuit Design, Testing Or Evaluating, Design Verification (e.g., Wiring Line Capacitance, Fan-out Checking, Minimum Path Width), Timing Analysis (e.g., Delay Time, Path Delay, Latch Timing)Method and apparatus for converting globally clock-gated circuits to locally clock-gated circuits description/claimsThe Patent Description & Claims data below is from USPTO Patent Application 20070220468, Method and apparatus for converting globally clock-gated circuits to locally clock-gated circuits. Brief Patent Description - Full Patent Description - Patent Application Claims
RELATED PATENT APPLICATION [0001] The present application is a divisional of U.S. Patent application Ser. No. 10/904,397 (Atty. Docket No. BUR920040011US1), filed on Nov. 8, 2004, and entitled, "Method and Apparatus for Converting Globally Clock-Gated Circuits to Locally Clock-Gated Circuits," which is incorporated herein by reference. BACKGROUND OF THE INVENTION [0002] 1. Technical Field [0003] The present invention relates to integrated circuit design methods in general, and, in particular, to a method for assigning clock-gated circuits within an integrated circuit design. Still more particularly, the present invention relates to a method for converting globally clock-gated circuits to locally clock-gated circuits within an integrated circuit design. [0004] 2. Description of Related Art [0005] A digital integrated circuit (IC) design typically employs many clock-gated circuits, such as flip-flops, latches, etc., that are periodically clocked by edges of a clock signal. Since there is a very large number (thousands or millions) of clock-gated circuits within an IC design, a single clock signal driver normally cannot directly supply a clock signal to all of the clock-gated circuits. Instead, a global clock tree having a set of buffers arranged in a tree-like network is utilized to supply clock signals to various clock-gated circuits. All circuits clocked by a global clock tree are considered as globally clock-gated circuits. [0006] In order to ensure proper synchronization between various parts of a circuit design, each clock signal edge should reach all synchronization points at substantially the same time. Thus, the time required for a clock signal edge to travel from its source to any clock-gated circuit should be substantially the same for all paths it follows through the global clock tree. The time required for a clock signal edge to work its way through the global clock tree from its source to a globally clock-gated circuit depends on many factors, such as the lengths of conductors in the path, the number of buffers the edge must pass through, the switching delay of each buffer, the amount of attenuation of the clock signal incurs between buffer stages, and the load each buffer must drive. Accordingly, the global clock tree needs to be balanced by ensuring that all clock signal paths between any two tree levels are of substantially similar length and impedance, that all buffers at any level of the global clock tree drive the same number of buffers or globally clock-gated circuits at the next level of the global clock tree, and that all buffers on any given level have similar characteristics. [0007] Generally speaking, global clock trees consume a relatively large amount of power. Global clock trees typically attribute to approximately 30-60% of the total power consumption of an IC design. In addition, the clocking of a global clock tree requires a rigid boundary between pipeline stages such that all logic must line up upon the boundaries. Thus, the ability to improve performance either in the current pipeline stage or in the next pipeline stage becomes locked to the clock boundary. The present disclosure provides a method for reducing overall clocking power consumption of an IC design such that additional flexibility in clock management can be achieved. SUMMARY OF THE INVENTION [0008] In accordance with a preferred embodiment of the present invention, a timing analysis is initially performed on an integrated circuit (IC) design to generate a slack time report for all globally clock-gated circuits within the IC design. Based on their respective slack time indicated in the slack time report, all globally clock-gated circuits that should be connected to locally generated clocks are identified. After disconnecting from a global clock tree, each of the identified globally clock-gated circuits is subsequently connected to a locally generated clock having a clock delay comparable to its slack time indicated in the slack time report. [0009] All features and advantages of the present invention will become apparent in the following detailed written description. BRIEF DESCRIPTION OF THE DRAWINGS [0010] The invention itself, as well as a preferred mode of use, further objects, and advantages thereof, will best be understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings, wherein: [0011] FIG. 1 is a block diagram of a conventional global clock tree for providing a common clock signal input to globally clock-gated circuits within an integrated circuit; [0012] FIG. 2 is a high-level logic flow diagram of a method for converting globally clock-gated circuits to locally clock-gated circuits, in accordance with a preferred embodiment of the present invention; [0013] FIG. 3 is a block diagram of a locally generated clock connected to two locally clock-gated circuits, in accordance with a preferred embodiment of the present invention; [0014] FIG. 4 is a high-level logic flow diagram of a method for determining whether or not a globally clock-gated circuit should be converted to a locally clock-gated circuit, in accordance with a preferred embodiment of the present invention; and [0015] FIG. 5 is a block diagram of a computer system in which a preferred embodiment of the present invention is incorporated. DETAILED DESCRIPTION OF A PREFERRED EMBODIMENT [0016] Referring now to the drawings and in particular to FIG. 1, there is depicted a block diagram of a conventional global clock tree for providing a common clock signal input to clock-gated circuits, such as flip-flops or latches, within an integrated circuit (IC). As shown, a global clock tree 10 includes an array of buffers 12-13 to fan out a CLOCK signal generated from a clock signal source 11. Typically, global clock tree 10 is locked tightly to a specific frequency with virtually zero jitter and clock drift across an entire IC design. In the embodiment shown in FIG. 1, two first stage buffers 12 fan the CLOCK signal out to four second stage buffers 13 that, in turn, fan the CLOCK signal out to thirty-two sinks 14. The number of buffer stages, the number of buffers per stage and the number of buffers or sinks each buffer drives are matters of design choice that depend on factors such as load capacity of buffers forming global clock tree 10, input impedance of the devices being driven, path impedances and allowable signal attenuation between stages, etc. [0017] Many circuits in the digital portion of an IC design change their logic states very infrequently but continue to be clocked in a synchronous fashion by a high-power clock tree, such as global clock tree 10 in FIG. 1, on every clock cycle. Such practice adds to unnecessary power consumption in clock distributions and latch activities. The present invention allows some globally clock-gated circuits within an IC design that switch infrequently to be converted to locally clock-gated circuits (i.e., using a locally generated delay clock). By reducing the number of simultaneous circuit switching within an IC design on the high-power clock tree or global clock tree, power consumption and chip noise can both be reduced. [0018] Although the localized delay clock still consumes power, an overall power reduction can be achieved if the new clock topology (i.e., one with a smaller global clock tree and the locally generated clock circuits) demands less power than the original unmodified global clock tree. Another advantage of reducing the number of globally clock-gated circuits locked to a global clock tree is that the launch noise of the set of globally clock-gated circuits driven on the global clock tree can also be reduced. Basically, the amount of simultaneous noise is reduced via a frequency spectrum spreading, which is an effect of using localized delay clocking. [0019] With reference now to FIG. 2, there is illustrated a high-level logic flow diagram of a method for converting globally clock-gated (or synchronous) circuits to locally clock-gated circuits, in accordance with a preferred embodiment of the present invention. Starting at block 21, a synchronous IC design having multiple globally clock-gated circuits, such as latches, flip-flops, etc., is simulated using functional test vectors that are deemed to cover a wide range of normal operating conditions. If no functional test vectors are available, the synchronous IC design may be simulated using automatic test pattern generation (ATPG) vectors. In either case, a logic circuit is formed with simulation results for the IC design in question. A timing analysis is then performed on the synchronous IC design, as shown in block 22. Continue reading about Method and apparatus for converting globally clock-gated circuits to locally clock-gated circuits... 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