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  Method and apparatus for computingUSPTO Application #: 20060004997Title: Method and apparatus for computing Abstract: A general purpose computing system comprises a novel apparatus and method for data processing. The computing system design of one application of the present invention includes an instruction pipe having a decompression circuit, a reprogrammable logic unit and a data bus. Instructions and data may be accessed via a shared bus or via a separate instruction bus and data bus. The decompression circuit accepts compressed instructions and memory management directives from the instruction bus, decompresses each instruction, and transmits the decompressed instruction to the reprogrammable logic unit. A software compiler is provided that accepts high level programming language source code and creates instructions that are coded for acceptance and execution by the reprogrammable logic unit. (end of abstract) Agent: Patrick Reilly - Santa Cruz, CA, US Inventor: Robert Keith Mykland USPTO Applicaton #: 20060004997 - Class: 712244000 (USPTO) Related Patent Categories: Electrical Computers And Digital Processing Systems: Processing Architectures And Instruction Processing (e.g., Processors), Processing Control, Branching (e.g., Delayed Branch, Loop Control, Branch Predict, Interrupt), Exeception Processing (e.g., Interrupts And Traps) The Patent Description & Claims data below is from USPTO Patent Application 20060004997. Brief Patent Description - Full Patent Description - Patent Application Claims
CONTINUATION-IN-PART [0001] This application is a continuation-in-part of U.S. Nonprovisional Utility patent application Ser. No. 10/128,940 filed on Apr. 24, 2002, which is a continuation-in-part of Provisional Patent Application Ser. No. 60/288,986 filed on May 4, 2001. This present Nonprovisional U.S. Utility patent application does hereby claim the benefit of the priority dates of the aforementioned U.S. Provisional Patent Application No. 60/288,986 and the U.S. Nonprovisional Utility patent application Ser. No. 10/128,940. The aforementioned U.S. Provisional Patent Application No. 60/288,986 and the U.S. Nonprovisional Utility patent application Ser. No. 10/128,940 are hereby incorporated by reference in their entirety herein and for all purposes in this Patent Application. BACKGROUND OF THE INVENTION [0002] The present invention relates to the architecture of computing systems. More particularly, the present invention addresses requirements to flexibly apply the capabilities of reprogrammable logic to the tasks of general purpose computing. FIELD OF THE INVENTION [0003] Electronic information storage and management is a fundamental aspect of most business and government activities in the industrialized world. Improvements in the art of computing system design and operating method can have profound effects in the operational efficiencies of numerous organizations and entire sectors of the world economy. [0004] It is well known in the art of computer systems design that an especially designed electronic logic circuit can often execute highly complex algorithms at rates superior to conventional general purpose computers. Yet the prior art applications and methods of using programmable logic fail to embody algorithms in programmable logic such that the reprogrammable logic can significantly and beneficially enable the general purpose application of high level computer language code and particularly event driven high level computer language code in the programming of these prior art systems. [0005] There is, therefore, a long felt need in the art of computer design to apply the advantages of dedicated logic circuits in the execution of programs derived from high level computer languages and under the control of commercially prevalent operating systems and particularly event driven operating systems. OBJECTS OF THE INVENTION [0006] It is an object of the present invention to provide a computer architecture that uses reprogrammable logic in software program execution. [0007] It is yet another object of the present invention to provide a computer system that includes reprogrammable logic and can execute at least one operating system. SUMMARY OF THE INVENTION [0008] According to the present invention, a computing device, or central processor, is provided. The preferred embodiment, or invented general-purpose computer, includes an integrated circuit computing device having an instruction pipehaving an optional instruction decompression circuit 20, a reprogrammable logic unit, an a data pipe. The data pipe may be coupled with a data bus and/or a data source, such as a memory device or bus. The data pipe may be optionally coupled with a data target, such as a data bus or a memory, to which the computational results of the RLU are communicated via the data pipe. Alternately, the data pipe may be comprised of a separate data input pipe and a data output pipe, wherein data is communicated to the RLU from the data source via the data input pipe, and output from the RLU, e.g., computational results, are communicated to the data target via the data output pipe. The instruction pipe may be coupled with an instruction source, such as a memory device or bus. The data source, the data target and/or the instruction source may be comprised within a single memory device. The instruction pipe and the data pipe may optionally include the same communications bus circuitry in whole or in part, whereby data and instructions may be transmitted via elements of the same communications bus either simultaneously on different elements or in a multiplexed technique via one or more, or all, shared resource components of the communications bus. In certain alternate preferred embodiments of the present invention, the operating system executed by the integrated circuit computing device may be MICROSOFT NT, MICROSOFT WINDOWS 98, MAC O/S 10, LINUX, or another suitable operating system known in the art. [0009] The data pipe is a processor used substantially for performing data movement. A computational array is a plurality of reconfigurable logic elements communicatively coupled. The inputs and outputs of a given reconfigurable logic element are communicatively coupled to a plurality of configurable logic elements using communicative coupling configuration data. The term reconfigurable is used here to include the meaning of being sequentially configurable a plurality of times. A reconfigurable logic element is a logic circuit whose behavior can be reconfigured with logic circuit behavior configuration data. A computational array instruction is: either/both logic circuit behavior configuration data and/or communicative coupling configuration data for all or any portion of the computational array. [0010] In certain alternate preferred methods of the present invention, the reprogrammable logic unit, or RLU, may include pluralities or multiplicities of specific functional types of electronic logic circuits, to include but not limited to invented muxes, invented cones, invented iterators and/or look up tables. The outputs of certain of these functional electronic logic circuit types may be reprogrammably placed in communication with the inputs of certain functional electronic logic circuits. In certain still alternate preferred embodiments of the present invention, one or more outputs of at least one functional electronic logic circuit may be reprogrammably linked to one or more inputs of the same, whereby a functional electronic logic circuit may provide an input from an output of itself. Certain yet alternate preferred embodiments of the present invention additionally provide for the programming of the internal logic state or states of a functional logic circuit as determined in part or in whole by the computations or direction of the functional logic circuit itself. [0011] The method of the present invention enables the application of reprogrammable logic circuits within an integrated computing circuit device in combination with the provision of instructions generated by a software compiler. The software compiler analyzes the original source code and generates instructions that program and reprogram the interconnects between the reprogrammable logic elements and enable or disable logic within the elements themselves in sequences that support the rapid execution of the commands specified by the source code. [0012] The instructions are software commands that are generated by a software compiler or another suitable means or method of generating or creating software machine code known in the art. The compiler may maintain a model of part or of the entire reprogrammable logic unit. The compiler accepts a source code and creates a series of instructions that enable the effective programming of the reprogrammable logic unit and cause the reprogrammable logic unit to execute the commands of the source code when the reprogrammable unit is executing the resultant instruction or series of instructions generated by the compilation of the source code. In certain preferred embodiments the source code may be in higher-level languages, such as C, C++, JAVA, or other suitable programming languages known in the art. [0013] Certain preferred embodiments of the present invention include novel and invented electrical circuits and novel and inventive combinations of the invented circuits that have newly invented circuits and/or prior art circuits. A newly invented data mux circuit, or mux, may be configured to effectively perform data processing of general logic and math data, it may be configured to effectively create partial products for multiplication operations, and/or to perform bit shifting or bit selection. A newly invented cone circuit, or cone, is useful for the digital data processing actions of parallel carry, parallel borrow, basic logic on a large number of inputs, and the counting of leading zeroes. A newly invented iterator circuit, or iterator, is useful for input/output actions to/from the data pipe and for storage of results from one execution cycle to subsequent execution cycles. Prior art look up tables and each of the newly invented mux, cone and iterator circuits are implemented solely or in combination in certain alternate preferred embodiments of the present invention. [0014] A preferred embodiment of the data mux circuit has three inputs (data) feeding into eight three-input AND gates enabled by eight bits of RAM (instruction space). Each of the AND gates has one of eight possible configurations of straight and inverted signals. [0015] Eight outputs of the eight AND gates may then be connected to an eight input OR gate, from which a single data logic level output is produced. Since only one of the AND gates can be high at any given time, the logic of this circuit can be embodied in eight multiple enable buffers tied to the eight RAM bits. The title of mux was chosen for this newly invented circuit from the fact that the input stage is logically a three to eight demultiplexer. One of the possibilities of certain preferred embodiments of the present invention is to provide a reconfigurable logic unit, or RLU, that does digital math and logic processing. Here are some of the functions that the mux may be configured to perform: [0016] Two or three input logic circuits, such as: [0017] A xor B is 0x66; [0018] A and B and C is 0x80; and [0019] A or B or C is 0xFE. [0020] Many useful digital math circuits, such as: [0021] Sum bit of an add is 0x96; [0022] Difference bit of a subtract is 0x69; and [0023] Carry bit of a Wallace tree node is 0xE8. [0024] A plurality of muxes can be configured to produce the results of partial products. Given the basic mux circuit described above, instead of the RAM bits feeding into the eight buffers, one could design a mux having the outputs of eight surrounding muxes (as one possibility) feeding into the eight buffers the mux. For a general partial product bit, the result could be programmed as follows: [0025] For multiplier bits A, B, and C and multiplicand bits X and Y: [0026] Mux 0 gives 0 and feeds into bit 0 of the master mux; [0027] Mux 1 gives Y and feeds into bit 1 of the master mux; [0028] Mux 2 gives Y and feeds into bit 2 of the master mux; [0029] Mux 3 gives X and feeds into bit 3 of the master mux; [0030] Mux 4 gives /X and feeds into bit 4 of the master mux; [0031] Mux 5 gives /Y and feeds into bit 5 of the master mux; [0032] Mux 6 gives /Y and feeds into bit 6 of the master mux; [0033] Mux 7 gives 0 and feeds into bit 7 of the master mux; and; [0034] The master mux buffers being controlled by A, B, C. Continue reading... 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