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Metal wiring pattern for memory devicesRelated Patent Categories: Semiconductor Device Manufacturing: Process, Coating With Electrically Or Thermally Conductive Material, To Form Ohmic Contact To Semiconductive Material, Contacting Multiple Semiconductive Regions (i.e., Interconnects), Multiple Metal Levels, Separated By Insulating Layer (i.e., Multiple Level Metallization)Metal wiring pattern for memory devices description/claimsThe Patent Description & Claims data below is from USPTO Patent Application 20060141765, Metal wiring pattern for memory devices. Brief Patent Description - Full Patent Description - Patent Application Claims
CROSS REFERENCE TO RELATED APPLICATIONS [0001] This application is a divisional of application Ser. No. 10/686,731, filed on Oct. 17, 2003 which is a divisional of application Ser. No. 09/805,913, filed on Mar. 15, 2001, now U.S. Pat. No. 6,664,634, the disclosures of which are herewith incorporated by reference in their entireties. FIELD OF THE INVENTION [0002] The present invention relates to an improved integrated circuit chip, and more specifically to the metalization patterns of a dynamic random access memory device. BACKGROUND OF THE INVENTION [0003] High component density and rapid signal transmission are both desirable in an integrated circuit memory device. As circuit density rises however, the conductive traces used to interconnect components must be made finer and placed closer together. Unfortunately, making traces finer and placing them closer together makes them less amenable to rapid signal transmission. [0004] Reducing the cross-section of a given conductor increases its resistance, and consequently its RC time constant. A higher RC time constant is reflected in lower signal transmission speed. Placing traces closer together increases the probability of crosstalk. This also effectively reduces the capacity of a line to transmit signals rapidly. There is thus a need to provide novel interconnect structures that allow rapid signal transmission across high-density integrated circuits. [0005] Different methods of forming conductors on integrated circuit memory devices are known in the art. In conventional practice, conductors have been implemented as buried polysilicon traces. These are formed by patterned doping of a semiconductor substrate. The resistance and capacitance of such traces are high, as compared with traces formed by other means. [0006] It is also known to form metallic interconnects by depositing a layer of metal over a substrate and selectively etching the layer to form a conductor pattern. [0007] The deposition of metal traces over a substrate assembly may also be accomplished by use of a damascene process. In the damascene process metal lines are deposited in grooves etched into a dielectric layer such as a substrate assembly, or insulating layer. Excess metal is then removed by chemical mechanical planarization (CMP). Once the excess metal has been removed only the metal that was deposited down within the grooves remains. This metal forms the interconnecting traces between devices. [0008] Depending on the configuration of the traces, the resistance and capacitance of buried polysilicon lines, or metal traces formed by various methods, tends to limit signal transmission speed. Signal crosstalk between conductors remains a problem. Accordingly, there is a need for new conductor structures and arrangements that improve signal transmission speed in the face of increasing component density. SUMMARY OF THE INVENTION [0009] The present invention addresses the need for reduced capacitance and increased trace conductivity in the metalization layers of integrated circuit devices, for example dynamic random access memory devices. The integrated circuit includes three layer metalization and various features, and trace layouts, offering improved system performance. [0010] In one aspect of the present invention, the use of buried polysilicon conductors as circuit traces is supplemented by three layers of metal traces deposited in layers above a substrate assembly and separated by layers of insulation. The substrate assembly includes doped active regions, and polysilicon plugs. By reducing the number of buried polysilicon conductor lines, and replacing them with metal traces, the integrated circuit reduces the trace resistance and capacitance of key traces. This increases the signal response speed for the circuit. [0011] In one aspect of the invention, I/O lines of an integrated circuit memory device are provided in a third layer of metalization. The lines cross four or eight memory blocks of an array in uninterrupted fashion from their respective points of origin to their respective points of termination. [0012] In another aspect of the present invention, column select lines of an integrated circuit memory device are disposed in a third layer of metalization above a memory array and in a second layer of metalization for a short span in the vicinity of an I/O line. [0013] In another aspect of the invention, discrete I/O lines of an integrated circuit memory device are separated from one another by interspersed control lines. The interspersed lines are selected such that signal transitions during operation of the memory device take place on the I/O lines out of phase with signal transitions taking place on the interspersed control lines. Consequently at the time of signal transitions of the I/O lines, known as column time, the interspersed control lines appear to be static. The static lines shield the I/O lines, that they separate from one another. They thus prevent capacitive interference between I/O lines during I/O line transitions. Likewise, the I/O lines are stable during transitions of the interspersed control lines, at row time. The result is that the I/O lines serve to shield the control lines from transients present on other control lines or non-I/O lines respectively. [0014] In another aspect of the invention, a low-impedance power bus for an integrated circuit memory device is provided by disposing power traces on substantially parallel regions of metalization in adjacent layers of metalization, and joining these regions with a plurality of conductive vias to form a power bus sandwich. [0015] In another aspect of the invention, a ground bus sandwich for an integrated circuit memory device is provided by disposing ground conductors, connected by a plurality of vias, in substantially parallel spaced relation, on two adjacent layers of metalization. [0016] In yet another aspect of the invention, the allocation of circuit traces in an integrated circuit memory device to a third layer of metalization allows for the provision of low trace density on the third layer. This low trace density permits greater spacing between traces, and accordingly thicker traces, since the aspect ratio of traces and the spaces therebetween is limited by the limitations of parallax and anisotropic etch processes. Accordingly, third layer traces may be formed that are both less resistive than first and second layer traces, because of increased cross section, and having less capacitive interaction with the underlying substrate assembly of the circuit. This results in third layer conductive traces with a reduced RC product, thus characterized by reduced signal propagation times. [0017] In yet another aspect, the invention includes a column select line of an integrated circuit memory device that, in the vicinity of a sense amplifier, is routed through a second metal layer, rather than a first metal layer, thereby allowing a substantially larger trace cross section. Consequently, the resistance of the trace is reduced, as are signal transmission times. [0018] In yet another aspect of the invention, column select lines of an integrated circuit memory device are disposed in a third layer of metalization substantially parallel to digit lines disposed in a first layer of metalization. A plurality of other metal traces are disposed in an intervening second layer of metalization with an orientation substantially perpendicular to both the digit lines below and the column lines above. As a result the digit lines are shielded by the intervening metal traces in the second layer of metalization from capacitive interference originating with signal transitions taking place on the column select lines in the third layer of metalization. It was previously necessary to arrange the column select lines in a serpentine configuration that crossed all digit lines. This promoted equal coupling between the column select line and all digit lines, thereby avoiding imbalance between digit lines. Now, however, it is possible to run a column select line in metal-3 linearly in parallel with digit lines. The result is a more direct, and hence a shorter, column select line path with resultant reduced capacitance and resistance, and increased signal transmission speed. [0019] In yet another aspect of the invention, the main power bus for an integrated circuit memory device is run, in continuous fashion on the second metal layer, through the wordline driver and gap cell regions of the integrated circuit. [0020] In yet another aspect of the invention, LT lines of an integrated circuit memory device are arranged so as to occupy, in different regions, three layers of metalization. An LT line is a global word line that spans an array, and is adapted to convey a decoded address signal to a wordline driver. Continue reading about Metal wiring pattern for memory devices... Full patent description for Metal wiring pattern for memory devices Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Metal wiring pattern for memory devices patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. Start now! - Receive info on patent apps like Metal wiring pattern for memory devices or other areas of interest. ### Previous Patent Application: Interlocking via for package via integrity Next Patent Application: Method of manufacturing wiring board Industry Class: Semiconductor device manufacturing: process ### FreshPatents.com Support Thank you for viewing the Metal wiring pattern for memory devices patent info. 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