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Metal interconnect layer of semiconductor device and method for forming a metal interconnect layerRelated Patent Categories: Semiconductor Device Manufacturing: Process, Coating With Electrically Or Thermally Conductive Material, To Form Ohmic Contact To Semiconductive Material, Contacting Multiple Semiconductive Regions (i.e., Interconnects)Metal interconnect layer of semiconductor device and method for forming a metal interconnect layer description/claimsThe Patent Description & Claims data below is from USPTO Patent Application 20060160351, Metal interconnect layer of semiconductor device and method for forming a metal interconnect layer. Brief Patent Description - Full Patent Description - Patent Application Claims
RELATED APPLICATIONS [0001] This application is a divisional of U.S. application Ser. No. 10/738,727, filed on Dec. 17, 2003, which is a divisional of U.S. application Ser. No. 09/879,556, filed on Jun. 12, 2001, now abandoned, which relies for priority upon Korean Patent Application No. 2000-64557, filed in the Korean Intellectual Property Office on Nov. 1, 2000, the contents of which are herein incorporated by reference in their entirety. BACKGROUND OF THE INVENTION [0002] 1. Field of the Invention [0003] The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a metal interconnect layer of a semiconductor device and a method for forming the metal interconnect layer. [0004] 2. Description of the Related Art [0005] For higher integration density and rapid operation of integrated circuit chips, semiconductor integration techniques have been advanced. The size of chips has been decreased with a smaller design rule to satisfy the need for high integration level. To increase the operation speed of chips, performance of transistors has been enhanced by reducing the parasitic resistance and parasitic capacitance of the transistors. [0006] With regard to interconnection techniques for semiconductor devices, it is significant to design a high-performance transistor with a minimum resistance and parasitic capacitance, such that an RC level (resistance.times.capacitance) of a semiconductor device having the capacitor is low. The resistivity of copper (Cu), 1.8 .mu..OMEGA.-cm, is lower than that of aluminum (Al), 2.7 .mu..OMEGA.-cm. Due to the low resistance of Cu, there is a thickness reduction effect when a metal interconnect layer is made of Cu. For this reason, use of Cu as a material for metal interconnect has proliferated to reduce interconnection resistance and parasitic capacitance with a 0.18 .mu.m or less design rule. [0007] FIGS. 1 and 2 illustrate the configuration of metal interconnects formed by a conventional damascene process. For the metal interconnects shown in FIGS. 1 and 2, the conductive layers are formed of Cu. In particular, a trench is formed in an interlevel dielectric (ILD) film, and a barrier layer 16 and a conductive layer 18 are deposited in sequence, filling the trench. Then, the semiconductor wafer 10 is subjected to chemical mechanical polishing. Such processes are collectively called "damascene processes." When a metal interconnect is formed by the conventional damascene process, a lifting of the conductive layer 18 in the trench may occur due to stress applied to the ILD film 12 during a subsequent thermal process. This problem is serious when the upper width of a trench is larger than the lower width, as shown in FIG. 2. When such lifting of a metal connection occurs in a trench, the contact between a via and the metal interconnect is unsatisfactory, so that normal operation of semiconductor chips is impossible. [0008] FIG. 3 illustrates lifting of a metal interconnect in a trench. As the trench angle (.theta.) in the ILD film becomes smaller, it is more likely that lifting of the conductive layer 18 will occur. SUMMARY OF THE INVENTION [0009] To solve the above problems, it is an object of the present invention to provide a metal interconnect layer of a semiconductor device that essentially does not lift from a trench. [0010] It is another object of the present invention to provide a method for forming a metal interconnect layer of a semiconductor device, which can prevent lifting of the metal interconnect layer from a trench. [0011] According to an aspect of the present invention, there is provided a metal interconnect layer of a semiconductor device. The interconnect layer includes a first upper portion having a first width and a second lower portion under the first upper portion. The lower portion has a second width which is larger than the first width of the upper portion of the interconnect. [0012] The metal interconnect layer can include a barrier layer deposited along an interlevel dielectric (ILD) film with a trench having a lower width and an upper width, the lower width being larger or wider than the upper width. The interconnect layer can also include a conductive layer deposited over the barrier layer filling the trench, the conductive layer having a lower width and an upper width, the lower width being wider or larger than the upper width. [0013] In one embodiment, the ILD film may be formed of a single insulation layer of a material selected from the group consisting of undoped silicate glass (USG) layer, silicon oxide fluoride (SiOF) layer, tetraethylorthosilicate (TEOS) layer, spin-on glass (SOG) layer and borophosphosilicate glass (BPSG). The thickness of an upper portion of the ILD film surrounding a portion of the trench with the upper width may be in the range of 20-70% of the thickness of the entire ILD film. [0014] In another embodiment, the ILD film comprises first and second insulation layers deposited in sequence, the trench being formed in the ILD film such that the portion of the trench formed in the first insulation layer is wider than the portion of the trench formed in the second insulation layer. The thickness of the second insulation layer may be in the range of 20-70% of the thickness of the entire ILD film including the first and second insulation layers. The second insulation layer may be formed of a USG layer, SiOF layer, TEOS layer, SOG layer or BPSG layer, and the first insulation layer can be formed of a flowable oxide (FOX) layer or hydride organic siloxane polymer (HOSP) layer having a higher etch rate than the second insulation layer. [0015] The barrier layer can be formed of a Ta layer, a TaN layer, a Ti layer, a TiN layer or a bilayer of these layers. The conductive layer can be formed of a Cu or a W layer. [0016] In another aspect, the present invention provides a metal interconnect layer for a semiconductor device, which includes a first upper portion having a first width, a second middle portion having a second width and a third lower portion having a third width. The third width is wider or larger than the first and second widths. [0017] In one embodiment, the metal interconnect layer comprises a barrier layer deposited along an ILD film with a trench having a lower width, a middle width and an upper width. The middle width is wider or larger than the upper and lower widths. The metal interconnect layer also includes a conductive layer deposited over the barrier layer filling the trench. The conductive layer has a lower width, a middle width and an upper width, the middle width being wider or larger than the upper and lower widths. [0018] The ILD film may be formed as a single layer with a material selected from the group consisting of USG layer, SiOF layer, TEOS layer, SOG layer and BPSG layer. The thickness of a middle portion of the ILD film surrounding a portion of the trench with the larger middle width may be in the range of 20-50% of the thickness of the entire ILD film. [0019] In another embodiment, the ILD film comprises first, second and third insulation layers deposited in sequence, the trench being formed in the ILD film such that the portion of the trench formed in the second insulation layer is wider than the portions formed in the first and third insulation layers. The thickness of the second insulation layer may be in the range of 20-50% of the thickness of the entire ILD film including the first, second and third insulation layers. Each of the first and third insulation layers may be formed of a USG layer, SiOF layer, TEOS layer, SOG layer or BPSG layer, and the second insulation layer can be formed of a FOX layer or HOSP layer having a higher etch rate than the first and third insulation layers. [0020] According to another aspect of the present invention, there is provided a method for forming a metal interconnect layer of a semiconductor device. In accordance with the method, an ILD film is formed over a semiconductor wafer. A photoresist pattern, defining a metal interconnect region is formed on the ILD film. A portion of the ILD film is etched using the photoresist pattern as an etch mask to form an initial relatively shallow trench, resulting in a polymer layer serving as an etch barrier being formed on the sidewalls of the shallow trench. Then, the remainder of the ILD film is etched using the photoresist pattern and the polymer layer on the shallow trench sidewalls as an etch mask, thereby resulting in a deeper trench whose lower width is larger than the upper width. Then, the photoresist pattern is removed. A barrier layer is formed along the semiconductor wafer and in the trench, and then a conductive layer is deposited over the barrier layer. The conductive layer is then polished by chemical mechanical polishing (CMP), such that the conductive layer remains within only the trench. [0021] In one embodiment, in etching a portion of the ILD film to form the initial relatively shallow trench, a hydrogen containing CF-based gas and an inert gas are used such that the polymer layer is formed on the initial trench sidewalls. In etching the remainder of the ILD film to deepen the trench, a non-hydrogen containing CF-based gas and an inert gas are used together with at oxygen and/or nitrogen. Continue reading about Metal interconnect layer of semiconductor device and method for forming a metal interconnect layer... Full patent description for Metal interconnect layer of semiconductor device and method for forming a metal interconnect layer Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Metal interconnect layer of semiconductor device and method for forming a metal interconnect layer patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. 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