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  Metal-insulator-metal capacitor and method of fabricating sameUSPTO Application #: 20080049378Title: Metal-insulator-metal capacitor and method of fabricating same Abstract: A metal-insulator-metal (MIM) capacitor including a metal layer, an insulating layer formed on the metal layer, at least a first opening and at least a second opening formed in the first insulating layer, a dielectric layer formed in the first opening, a conductive material deposited in the first and second openings, and a first metal plate formed over the first opening and a second metal plate formed over the second opening. A method for fabricating the MIM capacitor, includes forming the first metal layer, forming the insulating layer on the first metal layer, forming at least the first opening and at least the second opening in the first insulating layer, depositing a mask over the second opening, forming the dielectric layer in the first opening, removing the mask, depositing the conductive material in the first and second openings, and depositing a second metal layer over the first and second openings. MIM capacitors and methods of fabricating same are described, wherein the MIM capacitors are formed simultaneously with the BEOL interconnect and large density MIM capacitors are fabricated at low cost. (end of abstract) Agent: F. Chau & Associates, LLC - Woodbury, NY, US Inventors: Louis L. Hsu, Rajiv V. Joshi, Chun-Yung Sung USPTO Applicaton #: 20080049378 - Class: 361312000 (USPTO) The Patent Description & Claims data below is from USPTO Patent Application 20080049378. Brief Patent Description - Full Patent Description - Patent Application Claims
CROSS REFERENCE TO RELATED APPLICATIONS [0001] This application is a divisional of U.S. patent application Ser. No. 11/205,719, filed Aug. 17, 2005, which is a divisional of U.S. patent application Ser. No. 10/643,307, filed Aug. 19, 2003, now U.S. Pat. No. 6,964,908, the disclosures of which are incorporated by reference herein in their entireties. BACKGROUND OF THE INVENTION [0002] 1. Field of the Invention [0003] The present invention relates to a metal-insulator-metal capacitor and a method of fabricating same and, more particularly, to a metal-insulator-metal capacitor incorporating metal studs or vias to increase the density thereof and reduce manufacturing costs, and a method of fabricating same. [0004] 2. Description of the Related Art [0005] Contemporary integrated circuit design demands large capacitors having high density to meet the needs of higher density integrated circuits. Capacitors may be used for a number of functions, including, for example, as a reservoir capacitor for a charge pump circuit or for noise decoupling. [0006] Some known high density capacitors use a metal-insulator-metal (MIM) structure. MIM capacitors are valuable components in memory, logic and analog circuits. Some MIM capacitors are bulky planar devices introduced into integrated circuits at the back-end-of-line (BEOL) and require dielectric materials with low processing temperatures. The dielectric materials may include SiO.sub.2 or Si.sub.3N.sub.4 deposited using plasma enhanced chemical vapor deposition (PECVD) and have capacitance densities ranging from about 1 to 1.5 fF/.mu.m.sup.2. These capacitors, referred to as horizontal plate capacitors, demand large chip area. U.S. Pat. No. 5,926,359 to Greco et al., for example, relates to a known horizontal plate capacitor. [0007] The ongoing scaling of very large scale integration (VLSI) circuits requires a reduction of the planar area allocated to an MIM capacitor while maintaining the capacitance requirements. Thickness scaling of current materials has resulted in problems such as increases in leakage current and voltage linearity, and a reduction in lifetime reliability of thinner films. [0008] Building capacitors in the vertical direction is a known method of reducing the amount of chip area occupied by a capacitor. For example, a capacitor may be formed on the sidewalls and the bottom of a deep trench structure. See, e.g., U.S. Pat. No. 6,358,837 to Miller et al. According to known methods, the trenches are formed at the BEOL due to requirements of low temperature metal processing to avoid melting of the electrodes. However, in some instances, it has been suggested to form deep trenches in a silicon substrate and to form the electrodes with doped polysilicon or a metal having a high melting point, such as tungsten. A problem with the use of deep trenches is high processing costs. [0009] As an alternative to deep trenches, another vertical MIM capacitor utilizing a shallow trench structure, has been proposed. See, e.g., U.S. Pat. No. 6,329,234 to Ma et al. The shallow trench is formed by etching insulating material in the BEOL. Capacitors formed in the shallow trench structure have been referred to as semi-interdigitated MIM capacitors. A problem with the semi-interdigitated MIM capacitor is that the surface efficiency may be only 50-60%, which means that the semi-interdigitated MIM capacitor does not allow all the nodes to couple at all surfaces. [0010] Reduction in available area has also led to the introduction of alternative high dielectric constant materials such as Al.sub.2O.sub.3, Ta.sub.2O, HfO.sub.2 and laminate stacks thereof. See Hu, H, IEEE Elect. Dev. Lett., Vol. 23, No. 9, 2002. The introduction of the alternative materials may require integration processing, such as reactive ion etching (RIE) to pattern the MIM capacitor area. In some cases, the RIE patterning of the alternative materials requires plasma etching at elevated temperatures and/or a dual step process of plasma etching followed by a wet chemical etch. Such processing required when using the alternative materials increases manufacturing costs. For example, HfO2 is a material that is difficult to etch. See Sematech, "FEP Surface Preparation", Monthly Report, December, 2002. [0011] Therefore, there exists a need for a low-cost MIM capacitor and method of fabricating same, which can increase capacitor density and utilize some of the existing semiconductor processing steps so as to reduce integration cost. BRIEF SUMMARY OF THE INVENTION [0012] A method for fabricating a metal-insulator-metal capacitor, in accordance with the present invention, includes forming a first metal layer, forming a first insulating layer on the first metal layer, forming at least a first opening and at least a second opening in the first insulating layer, depositing a mask over the second opening, forming a first dielectric layer in the first opening, removing the mask, depositing a first conductive material in the first and second openings, depositing a second metal layer over the first and second openings. [0013] In alternate embodiments, the method may include forming a polish stop layer on the first insulating layer and performing chemical mechanical polishing on the conductive material. The first and second openings may be formed by etching the insulating layer down to the first metal layer. The second metal layer may consist of a first plate formed over the first opening and a second plate formed over the second opening. The first and second metal layers may be formed from one of aluminum, cooper and tungsten. The mask may be formed from one of a polymer or resist material. The first conductive material may be formed from one of aluminum, cooper and tungsten. The first dielectric layer may be formed from one of chemical vapor deposition oxide and chemical vapor deposition nitride. The method may also include forming a second insulating layer on the second metal layer, forming at least a third opening and at least a fourth opening in the second insulating layer, forming a second dielectric layer in the third opening, depositing a second conductive material in the third and fourth openings, and forming a third metal layer over the third and fourth openings. [0014] Another method for fabricating a metal-insulator-metal capacitor, in accordance with the present invention includes forming a first metal layer, forming an insulating layer on the first metal layer, forming at least a first via and at least a second via in the insulting layer and on the first metal layer, depositing a mask over the second via and a predetermined portion of the insulating layer, etching an exposed area of the insulating layer down to the first metal layer, removing the mask, forming a dielectric layer on a remaining area after etching and removal of the mask, selectively removing a predetermined portion of the dielectric layer, and depositing a second metal layer over the first and second vias. [0015] In alternate embodiments, the first and second vias may include conductive material deposited therein, a predetermined portion of the dielectric layer may cover at least the second via, and the second metal layer may be patterned to form a first plate over the first via and a second plate over the second via. [0016] Another method for fabricating a metal-insulator-metal capacitor, in accordance with the present invention, includes forming a first metal layer, forming an insulating layer on the first metal layer, forming at least a first opening and at least a second opening in the insulating layer, depositing a sidewall liner material on the insulating layer and in the first and second openings, removing a predetermined portion of the sidewall liner material to form spacers on each sidewall of the first and second openings, forming a dielectric layer on the insulating layer, and on the spacers and exposed portions of the first metal layer in the first and second openings, depositing a mask over the first opening; removing the dielectric layer from the second opening, filling the second opening with a conductive material, and depositing a second metal layer over and in the first opening and over the second opening including the conductive material. [0017] In alternate embodiments, the first and second openings may be formed by etching the insulating layer down to the first metal layer, the sidewall liner material may be TiN, and the step of removing a predetermined portion of the sidewall liner material may be performed by etching the sidewall liner material. The step of removing the dielectric layer may be performed by selective etching and the conductive material may be tungsten. The method may further include patterning the second metal layer to form a first plate over and in the first opening and a second plate over the second opening including the conductive material. [0018] A metal-insulator-metal capacitor, in accordance with the present invention includes a metal layer, an insulating layer formed on the metal layer, at least a first opening and at least a second opening formed in the first insulating layer, a dielectric layer formed in the first opening, a conductive material deposited in the first and second openings, and a first metal plate formed over the first opening and a second metal plate formed over the second opening. [0019] In alternate embodiments, the metal-insulator-metal capacitor may include a polish stop layer formed on the insulating layer and the metal layer and the first and second metal plates may be formed from one of aluminum, copper and tungsten. The conductive material may be formed from one of aluminum, copper and tungsten and the dielectric layer may be formed from one of chemical vapor deposition oxide and chemical vapor deposition nitride. [0020] Another metal-insulator-metal capacitor, in accordance with the present invention, includes a metal layer, an insulating layer formed on the metal layer, at least a first via and at least a second via formed in the insulting layer and on the metal layer, a dielectric layer formed on the first via and on an exposed area of the metal layer, and a first metal plate formed over the first via and a second metal plate formed over the second via. [0021] In alternate embodiments, the first and second vias may include conductive material deposited therein and the metal-insulator-metal capacitor may further include a polish stop layer formed on the insulating layer. Continue reading... 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