| Memory interface methods and apparatus -> Monitor Keywords |
|
|
  Memory interface methods and apparatusUSPTO Application #: 20060193188Title: Memory interface methods and apparatus Abstract: Memory interface methods and apparatus for processing source synchronous data from a memory device (DRAM). The methods and apparatus synchronously transfer data from the memory device to a memory controller even though the time variability of read return strobe signals is greater than one clock cycle. (end of abstract) Agent: Hewlett Packard Company - Fort Collins, CO, US Inventors: Jonathan Q. Smela, Michael K. Tayler USPTO Applicaton #: 20060193188 - Class: 365221000 (USPTO) The Patent Description & Claims data below is from USPTO Patent Application 20060193188. Brief Patent Description - Full Patent Description - Patent Application Claims
TECHNICAL FIELD [0001] The present invention relates generally to memory interface methods and apparatus. BACKGROUND [0002] Handling of source synchronous data from a memory device, such as a DRAM, is an important design challenge for a memory interface. The challenge stems from the time variability of a returning strobe signal because of factors such as process, voltage, temperature (PVT), board trace variation and clock uncertainties to name a few. Due to these factors, there can be significant variability between the earliest and latest possible times at which strobe signals start transitioning at an agent interface (i.e., interface between a control chip or controller and the DRAM). [0003] The Double Data Rate (DDR2) protocol stipulates that strobe signals driven by the DRAM have a preamble of one clock cycle. This preamble is defined as the time period preceding the first strobe signal edge when DQS_H (active high strobe signal) is low and DQS_L (active low strobe signal) is high. [0004] In previous memory subsystems developed by the assignee of the present invention (such as for a zx1 chipset), the time variability for the returning strobe signals is less than one clock cycle. This small variability allows a memory controller to generate a core synchronous signal that is guaranteed to be within the preamble of both the earliest and latest possible strobe signals. This core synchronous signal enables internal circuitry of a read data state machine (internal to the core) to begin responding to the input strobe. The result is a core synchronous control scheme that guarantees a deterministic state of the read data state machine. [0005] Through analysis of the memory subsystem in a zx2 chipset developed by the assignee of the present invention, it has been determined that the time variability of read return strobe signals is greater than one clock cycle and that the previously-developed methodology could not be used. BRIEF DESCRIPTION OF THE DRAWINGS [0006] The various features and advantages of embodiments of the present invention may be more readily understood with reference to the following detailed description taken in conjunction with the accompanying drawings, wherein like reference numerals designate like structural elements, and in which: [0007] FIG. 1 is a block diagram showing a portion of an exemplary embodiment of a computer system incorporating the present invention; [0008] FIG. 2 illustrates an exemplary embodiment of strobe gating apparatus in accordance with the principles of the present invention; [0009] FIG. 3 illustrates an exemplary embodiment of a shift register employed in the apparatus shown in FIG. 1; [0010] FIG. 4 illustrates an exemplary embodiment of a data FIFO employed in the apparatus shown in FIG. 1; [0011] FIG. 5 illustrates 1/4 cycle resolution and shift register timing diagram for the apparatus shown in FIG. 1; [0012] FIG. 6 illustrates an exemplary strobe variation timing diagram for the apparatus shown in FIG. 1; and [0013] FIG. 7 is a flow diagram that illustrates an exemplary embodiment of a method in accordance with the principles of the present invention. DETAILED DESCRIPTION [0014] Referring to the drawing figures, FIG. 1 is a block diagram showing a portion of an exemplary embodiment of a computer system 10 incorporating the present invention. The exemplary system 10 includes an agent integrated circuit chip 11 that comprises a memory controller 12, a bus interface circuit 13 and an 10 controller 14. The memory controller 12 is coupled to a memory device 15, such as a dual inline memory module (DIMM) 15 comprising DRAM chips 15. Address/control lines, data signal (DQ) lines and strobe signal (DQS) lines of a memory bus couple the memory controller 12 to the memory device 15. [0015] FIG. 2 illustrates an exemplary embodiment of strobe gating apparatus 16 (or strobe gating logic 16) in accordance with the principles of the present invention. More particularly, FIG. 2 shows exemplary strobe gating logic 16 located in pads of an agent chip which communicates to the DDR2 memory device 15. The strobe gating logic 16 communicates with the "outside world" (i.e., DIMM 15) and to the "inside world" (i.e., the memory controller 12 inside the agent chip 11). [0016] As is illustrated in FIG. 2, the strobe gating apparatus 16 comprises a data receiver 17 that receives a voltage reference signal (Vref) and data signals (DQ) output by the memory device 15. The output of the data receiver 17 is coupled to a data first-in, first-out (FIFO) circuit 18 (data FIFO 18). The output of the data FIFO 18 is coupled by way of the memory controller 12 and bus interface circuit 13 to an internal logic core that comprises a read data state machine. Read return strobe signals (DQS), comprising high and low strobe signals (DQS_H, DQS_L), are input to the strobe gating apparatus 16 by way a differential strobe receiver 22. The strobe receiver 22 outputs a complimentary strobe signal pair (STB_H, STB_L) that are processed to produce a gate that is synchronous to each individual strobe signal. The read return strobe signals (DQS) are also input to a preamble detector 21. [0017] The strobe gating apparatus 16 addresses the problem in DDR2 memory devices 15 wherein the time variability of read return strobe signals (DQS) output by the memory device 15 is greater than one clock cycle. The strobe gating apparatus 16 provides for core synchronous control that guarantees a deterministic state of the read data state machine. [0018] In particular, the strobe gating apparatus 16 handles the time variability of the read return strobe signals (DQS). In general, the strobe gate apparatus 16 generates masking signals that masks input strobe signals (DQS) until the beginning of preambles of the strobe signals, unmasks the strobe signals during a source driven transaction from the memory device 15, and masks the strobe signals at the end of the transaction. The result is a gate that is synchronous to each individual strobe signal which provides for a memory interface or subsystem (memory controller 12, memory bus, DRAM 15) that can tolerate as much a one and one half clock cycles of time variation. [0019] In order to provide accurate control of the strobe gate, a variable phase read clock, IORCK, is used to register core control signals. The read clock can have a 0, 90, 180 or 270 degree phase shift relative to a memory controller clock in the core. The variable phase clock allows quarter clock cycle resolution on core-to-pad control signal timing without requiring a clock whose frequency is 4 times the core memory controller clock. [0020] IOMCK represents a clock with a 0 phase relationship to a core memory controller clock. Each timing critical signal from the core is captured by a flip-flop 26 that is clocked by IOMCK. However, since the nominal returning strobe signal may not be aligned to the core clock, a flip-flop 27 controlled by the variable phase read clock, IORCK, is employed. The flip-flops 26, 27 output a core driven signal (rcv_on_pad or spc_stb_reset_rck) with a quarter clock cycle resolution to the nominal strobe edge. FIG. 5, the timing relationship for rcv_on_pad and spc_stb_reset_rck is illustrated for a read clock that is 180 degrees out of phase to IOMCK. The appropriate core driven signal is selectively gated using an AND gate 28 and NAND gate 29 Referring to a gate flip-flop 23 or gate control register 23. Continue reading... Full patent description for Memory interface methods and apparatus Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Memory interface methods and apparatus patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. Start now! - Receive info on patent apps like Memory interface methods and apparatus or other areas of interest. ### Previous Patent Application: Disk drive unit having reduced electrical power consumption Next Patent Application: Multi-memory chip and data transfer method capable of directly transferring data between internal memory devices Industry Class: Static information storage and retrieval ### FreshPatents.com Support Thank you for viewing the Memory interface methods and apparatus patent info. IP-related news and info Results in 4.94023 seconds Other interesting Feshpatents.com categories: Novartis , Pfizer , Philips , Polaroid , Procter & Gamble , |
||
