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  MemoryUSPTO Application #: 20060067139Title: Memory Abstract: A memory capable of suppressing disturbance is provided. This memory comprises a bit line, a word line arranged to intersect with the bit line and first storage means connected between the bit line and the word line, and applies prescribed reverse voltages to at least non-selected first storage means connected to a non-selected word line substantially identical times respectively or substantially applies no voltage through a read operation and a rewrite operation. (end of abstract) Agent: Arent Fox PLLC - Washington, DC, US Inventors: Naofumi Sakai, Yoh Takano USPTO Applicaton #: 20060067139 - Class: 365189090 (USPTO) The Patent Description & Claims data below is from USPTO Patent Application 20060067139. Brief Patent Description - Full Patent Description - Patent Application Claims
[0001] This is a Divisional Application, which claims the benefit of pending U.S. patent application Ser. No. 10/792,926 filed, Mar. 5, 2004. The disclosure of the prior application is hereby incorporated in its entirety by reference. BACKGROUND OF THE INVENTION [0002] 1. Field of the Invention [0003] The present invention relates to a memory, and more particularly, it relates to a memory having capacitance means and resistance means. [0004] 2. Description of the Background Art [0005] A method of reducing disturbance caused in a non-selected cell of a one-transistor ferroelectric memory is proposed in general. For example, Japanese Patent Laying-Open No. 10-64255 (1998) proposes such a method of reducing disturbance. In a data writing step disclosed in Japanese Patent Laying-Open No. 10-64255, voltages +V, 1/3 V, 0 V and 2/3 V are applied to a word line of a selected cell, the remaining word cells, a bit line of the selected cell and the remaining bit lines respectively as a first procedure. Then, voltages 0 V, 1/3 V, 1/3 V and 0 V are applied to the word line of the selected cell, the remaining word lines, the bit line of the selected cell and the remaining bit lines respectively as a second procedure. When voltages -V, -1/3 V, 0 V and -2/3 V are alternatively applied to the word line of the selected cell, the remaining word lines, the bit line of the selected cell and the remaining bit lines respectively in the aforementioned first procedure, voltages 0 V, -1/3 V, -1/3 V and 0 V are applied to the word line of the selected cell, the remaining word lines, the bit line of the selected cell and the remaining bit lines respectively in the second procedure carried out subsequently to the first procedure. Thus, the voltages 1/3 V and -1/3 V different in polarity to each other are applied to most non-selected cells single times respectively through the first and second procedures, whereby disturbance can be remarkably suppressed in data writing. [0006] In the aforementioned technique disclosed in Japanese Patent Laying-open No. 10-64255, however, no voltage is applied to those of the non-selected cells sharing the word and bit lines with the selected cell in the second procedure, and hence disturbance of these cells cannot be avoided. Further, Japanese Patent Laying-Open No. 10-64255 describes absolutely no method of suppressing disturbance in reading. SUMMARY OF THE INVENTION [0007] The present invention has been proposed in order to solve the aforementioned problems, and an object thereof is to provide a memory capable of suppressing disturbance. [0008] In order to attain the aforementioned object, a memory according to a first aspect of the present invention comprises a bit line, a word line arranged to intersect with the bit line and first storage means connected between the bit line and the word line for holding first data or second data, and applies a voltage pulse supplying an electric field in a first direction and another voltage pulse supplying another electric field in a direction opposite to the first direction to at least non-selected first storage means other than selected first storage means connected to a selected word line substantially identical times respectively or substantially applies no voltage pulse through a read operation and a rewrite operation consisting of a plurality of operations performed on the selected first storage means. [0009] The memory according to the first aspect, applying the voltage pulse supplying the electric field in the first direction and the other voltage pulse supplying the other electric field in the direction opposite to the first direction to at least all first storage means connected to a word line other than the selected word line substantially identical times respectively or substantially applying no voltage pulse through the read operation and the rewrite operation as hereinabove described, can suppress polarization deterioration in at least all non-selected first storage means connected to the word line other than the selected word line in the read operation. Thus, the memory can inhibit the first storage means from disturbance in the read operation. [0010] In the aforementioned memory according to the first aspect, the read operation and the rewrite operation consisting of the plurality of operations performed on the selected first storage means preferably include the read operation, an operation of writing the first data in the selected first storage means from which the second data has been read in the read operation and an operation of thereafter writing the second data in the selected first storage means from which the second data has been read in the read operation, and the memory preferably applies the voltage pulse supplying the electric field in the first direction and the other voltage pulse supplying the other electric field in the direction opposite to the first direction to the selected first storage means from which the first data has been read in the read operation substantially identical times respectively or substantially applying no voltage pulse through the operation of writing the first data and the operation of writing the second data. According to this structure, the memory, applying the voltage pulse supplying the electric field in the first direction and the other voltage pulse supplying the other electric field in the direction opposite to the first direction to the selected first storage means from which the first data has been read among the selected storage means connected to the selected word line substantially identical times respectively or substantially applying no voltage pulse, can suppress polarization deterioration also as to the first storage means from which the first data has been read among memory cells connected to the selected word line. Thus, the memory can suppress disturbance in the read operation as to not only the non-selected first storage means but also the first storage means from which the first data has been read among the first storage means connected to the selected word line. [0011] The aforementioned memory according to the first aspect preferably applies the voltage pulse supplying the electric field in the first direction and the other voltage pulse supplying the other electric field in the direction opposite to the first direction to at least substantially all non-selected first storage means single times respectively through the read operation and the rewrite operation. According to this structure, the memory can easily suppress polarization deterioration in the read operation in at least substantially all non-selected first storage means. [0012] In this case, the memory preferably applies the voltage pulse supplying the electric field in the first direction and the other voltage pulse supplying the other electric field in the direction opposite to the first direction also to the selected first storage means storing the first data single times respectively in addition to the non-selected first storage means through the read operation and the rewrite operation. According to this structure, the memory can easily suppress polarization deterioration in the read operation also in the selected first storage means storing the first data. [0013] The aforementioned memory according to the first aspect preferably applies the voltage pulse supplying the electric field in the first direction for a first period and applies the other voltage pulse supplying the other electric field in the direction opposite to the first direction for a second period, and the first period and the second period are preferably substantially equal to each other. According to this structure, the memory can substantially equalize a variation of a polarization quantity caused by the voltage pulse supplying the electric field in the first direction and that caused by the voltage pulse supplying the electric field in the direction opposite to the first direction with each other with respect to at least substantially all non-selected first storage means. [0014] The aforementioned memory according to the first aspect may apply a prescribed voltage to the selected first storage means while applying a voltage of m/n (m, n: positive integers) of the prescribed voltage to the non-selected first storage means in the read operation and the rewrite operation. [0015] In this case, the memory may apply a voltage of either substantially 1/3 or substantially 1/2 of the prescribed voltage to the non-selected first storage means. [0016] The aforementioned memory according to the first aspect may start the read operation after setting the word line and the bit line to substantially identical potentials. [0017] The aforementioned memory according to the first aspect preferably brings the bit line into a floating state in the read operation and thereafter sets the bit line to a fixed potential. According to this structure, the memory applies no voltage to all non-selected first storage means connected to the word line other than the selected word line in the read operation by equalizing the fixed potential of the bit line with the potential of the word line other than the selected word line. Therefore, the memory can inhibit all non-selected first storage means connected to the word line other than the selected word line from disturbance in the read operation. [0018] In this case, the memory preferably sets a period for bringing the bit line into a floating state in the read operation to a short period for sufficiently reducing a variation of the polarization quantity of the non-selected first storage means in the period as compared with a variation of the polarization quantity of the non-selected first storage means in the rewrite operation. According to this structure, the memory can easily reduce the variation of the polarization quantity caused in the non-selected first storage means in the period for bringing the bit line into the floating state in the read operation to a level substantially negligible with respect to the variation of the polarization quantity caused in the non-selected storage means in the rewrite operation. [0019] The aforementioned memory according to the first aspect preferably further comprises a read data determination circuit amplifying a voltage caused on the bit line in the read operation and thereafter comparing the amplified voltage with a reference voltage thereby determining whether data read from the selected first storage means is the first data or the second data. According to this structure, the memory can set the reference voltage to an intermediate level between a voltage obtained by amplifying a first data read voltage caused on the bit line and a voltage obtained by amplifying a second data read voltage in the read operation, whereby the range of the voltage to be set as the reference voltage is increased as compared with a case of comparing the voltage caused on the bit line in the read operation with the reference voltage in an unamplified state. Thus, the memory can easily generate the reference voltage. [0020] The aforementioned memory according to the first aspect may further comprise second storage means provided separately from the first storage means for storing data of reversed polarity to data stored in corresponding first storage means and compare a voltage caused on the bit line in the read operation with a reference voltage generated by reading data from the second storage means thereby determining whether data read from the selected first storage means is the first data or the second data. [0021] In the aforementioned memory according to the first aspect, the first storage means preferably includes a ferroelectric film. According to this structure, the memory can inhibit the first storage means including the ferroelectric film from disturbance in the read operation. [0022] In the aforementioned memory according to the first aspect, the first storage means preferably includes a resistive element. According to this structure, the memory can inhibit the first storage means including the resistive element from disturbance in the read operation. Continue reading... Full patent description for Memory Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Memory patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. Start now! - Receive info on patent apps like Memory or other areas of interest. ### Previous Patent Application: Low leakage and leakage tolerant stack free multi-ported register file Next Patent Application: Semiconductor device and method of forming a semiconductor device Industry Class: Static information storage and retrieval ### FreshPatents.com Support Thank you for viewing the Memory patent info. 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