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  Memory device with emulated characteristicsUSPTO Application #: 20080103753Title: Memory device with emulated characteristics Abstract: A memory subsystem is provided including an interface circuit adapted for communication with a system and a majority of address or control signals of a first number of memory circuits. The interface circuit includes emulation logic for emulating at least one memory circuit of a second number. (end of abstract) Agent: Zilka-kotab, PC- Mrm1 - San Jose, CA, US Inventors: Suresh Natarajan Rajan, Keith R. Schakel, Michael John Sebastian Smith, David T. Wang, Frederick Daniel Weber USPTO Applicaton #: 20080103753 - Class: 703023000 (USPTO) Related Patent Categories: Data Processing: Structural Design, Modeling, Simulation, And Emulation, Emulation The Patent Description & Claims data below is from USPTO Patent Application 20080103753. Brief Patent Description - Full Patent Description - Patent Application Claims
RELATED APPLICATION [0001] This application is a continuation of commonly-assigned U.S. patent application Ser. No. 11/762,010 entitled "Memory Device with Emulated Characteristics" filed Jun. 12, 2007 by Rajan, et al., which, in turn, is a continuation-in-part of commonly-assigned U.S. patent application Ser. No. 11/461,420 entitled "System and Method for Simulating a Different Number of Memory Circuits" filed Jul. 31, 2006 by Rajan, et al., which are incorporated by reference as if fully set forth herein. BACKGROUND OF THE INVENTION [0002] 1. Technical Field of the Invention [0003] This invention relates generally to digital memory such as used in computers, and more specifically to organization and design of memory modules such as DIMMs. [0004] 2. Background Art [0005] Digital memories are utilized in a wide variety of electronic systems, such as personal computers, workstations, servers, consumer electronics, printers, televisions, and so forth. Digital memories are manufactured as monolithic integrated circuits ("ICs" or "chips"). Digital memories come in several types, such as dynamic random access memory (DRAM), static random access memory (SRAM), flash memory, electrically erasable programmable read only memory (EEPROM), and so forth. [0006] In some systems, the memory chips are coupled directly into the system such as by being soldered directly to the system's main motherboard. In other systems, groups of memory chips are first coupled into memory modules, such as dual in-line memory modules (DIMMs), which are in turn coupled into a system by means of slots, sockets, or other connectors. Some types of memory modules include not only the memory chips themselves, but also some additional logic which interfaces the memory chips to the system. This logic may perform a variety of low level functions, such as buffering or latching signals between the chips and the system, but it may also perform higher level functions, such as telling the system what are the characteristics of the memory chips. These characteristics may include, for example, memory capacity, speed, latency, interface protocol, and so forth. [0007] Memory capacity requirements of such systems are increasing rapidly. However, other industry trends such as higher memory bus speeds, small form factor machines, etc. are reducing the number of memory module slots, sockets, connectors, etc. that are available in such systems. There is, therefore, pressure for manufacturers to use large capacity memory modules in such systems. [0008] However, there is also an exponential relationship between a memory chip's capacity and its price. As a result, large capacity memory modules may be cost prohibitive in some systems. [0009] What is needed, then, is an effective way to make use of low cost memory chips in manufacturing high capacity memory modules. SUMMARY [0010] A memory subsystem is provided including an interface circuit adapted for communication with a system and a majority of address or control signals of a first number of memory circuits. The interface circuit includes emulation logic for emulating at least one memory circuit of a second number. BRIEF DESCRIPTION OF THE DRAWINGS [0011] FIG. 1 shows a system coupled to multiple memory circuits and an interface circuit according to one embodiment of this invention. [0012] FIG. 2 shows a buffered stack of DRAM circuits each having a dedicated data path from the buffer chip and sharing a single address, control, and clock bus. [0013] FIG. 3 shows a buffered stack of DRAM circuits having two address, control, and clock busses and two data busses. [0014] FIG. 4 shows a buffered stack of DRAM circuits having one address, control, and clock bus and two data busses. [0015] FIG. 5 shows a buffered stack of DRAM circuits having one address, control, and clock bus and one data bus. [0016] FIG. 6 shows a buffered stack of DRAM circuits in which the buffer chip is located in the middle of the stack of DRAM chips. [0017] FIG. 7 is a flow chart showing one method of storing information. [0018] FIG. 8 shows a high capacity DIMM using buffered stacks of DRAM chips according to one embodiment of this invention. [0019] FIG. 9 is a timing diagram showing one embodiment of how the buffer chip makes a buffered stack of DRAM circuits appear to the system or memory controller to use longer column address strobe (CAS) latency DRAM chips than is actually used by the physical DRAM chips. [0020] FIG. 10 shows a timing diagram showing the write data timing expected by DRAM in a buffered stack, in accordance with another embodiment of this invention. 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