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Memory device and method of manufacturing the sameMemory device and method of manufacturing the same description/claimsThe Patent Description & Claims data below is from USPTO Patent Application 20070202648, Memory device and method of manufacturing the same. Brief Patent Description - Full Patent Description - Patent Application Claims
PRIORITY STATEMENT [0001]This application claims priority under 35 U.S.C. .sctn.119 to Korean Patent Application No. 10-2006-0019302, filed on Feb. 28, 2006 and Korean Patent Application No. 10-2006-0126409, filed on Dec. 12, 2006, in the Korean Intellectual Property Office (KIPO), the entire contents of which are incorporated herein by reference. BACKGROUND [0002]1. Field [0003]Example embodiments relate to a memory device including nanocrystals and methods of manufacturing and operating the memory device. Other example embodiments relate to a memory device including a polyelectrolyte film and nanocrystals and methods of manufacturing and operating the memory device. [0004]2. Description of the Related Art [0005]A memory device using a semiconductor may include, as basic elements, a transistor that functions as a switch to provide a path for a current when recording or reading information whereby the transistor may be placed in a capacitor, and a capacitor that preserves stored charges. A transistor may have a relatively high transconductance in order for an improved amount of current to flow. Conventionally, a metal oxide semiconductor field effect transistor (MOSFET) having a relatively high transconductance may often be used as a switching device of a semiconductor memory device. A MOSFET may include, as basic elements, a gate electrode formed of multi-crystalline silicon, and source and drain electrodes formed of doped crystalline silicon. [0006]As information equipment develops, research on reducing the size of memory devices is being conducted in order to obtain relatively highly integrated memory devices, thereby increasing the number of integrated memory devices per unit surface area. When such highly integrated memory devices are used, the signal transmission time between devices may be reduced and thus an improved amount of information may be processed at a relatively high speed. In a conventional MOSFET, the amount of heat generated in the MOSFET may be improved, and thus when the integration of the memory device increases, the device may melt or function undesirably. A single electron device (SED) has been developed to solve such problems. Ann SED may use electrical signals by transmitting one electron. It may be necessary to develop a device to precisely control the transmission of the electron. One material satisfying this requirement may be nanocrystals. A nanocrystal may be a material composed of a metal and/or semiconductor, having a smaller size than a Bohr exciton radius, for example, about a few nanometers. There may be a greater amount of electrons in the nanocrystals, but the number of free electrons in the nanocrystals may be limited to the range of about 1 to about 100. [0007]The energy potential of the electrons of the nanocrystals may be discontinuously limited and thus the nanocrystals may show different electrical and optical properties from the nanocrystals composed of a metal and/or semiconductor that may be in a bulk state, which forms a continuous band. Conventionally, various conductors and nonconductors may have to be mixed in order to obtain a predetermined or given band gap. Nanocrystals may have different energy potentials which vary according to the size of the nanocrystals, and thus the band gap may be controlled by changing the size. [0008]Also, unlike a bulk type semiconductor, the amount of energy required to add electrons may not be uniform but may change stepwise according to the addition of each electron. A Coulomb blockade effect, in which a previously present electron disturbs the addition of a new electron, may occur. When there are a predetermined or given number of electrons needed for crystals, an additional transfer of electrons by tunneling may be blocked. When the size of the nanocrystals is less than about 10 nm theoretically, a single electron may be transferred. Because the number of transferred electrons is smaller, the amount of generated heat accompanying the transferred electrons may also be relatively small, and this may enable a reduction in the size of the device. [0009]The nanocrystals may be used in a relatively small device when combined with a transistor. Research into a memory device using nanocrystals may be conducted. Conventional nanocrystals used in memory devices may be manufactured by a heat treatment. Nanocrystals having a relatively high melting point may not be treated with heat. Even though the nanocrystals are manufactured by heat treatment, the size of the nanocrystals may not be uniform, which may deteriorate the device characteristic of the manufactured memory device. SUMMARY [0010]Example embodiments provide a method of manufacturing a memory device using polyelectrolytes. Other example embodiments provide a memory device including a tunneling oxide layer. Other example embodiments provide a method of operating a memory device. [0011]According to example embodiments, a method of manufacturing a memory device may include providing a substrate, forming at least one tunneling oxide layer on a surface of the substrate, forming a polyelectrolyte layer on a surface of the at least one tunneling oxide layer, arranging nanocrystals on the polyelectrolyte layer and forming a control oxide layer on the surface of the at least one tunneling oxide layer in which the nanocrystals may be arranged. [0012]According to example embodiments, the at least one tunneling oxide layer may include first and second tunneling oxide layers. The method may further include forming a source and drain region on the surface of the substrate and forming a control gate on the surface of the control oxide layer. According to example embodiments, the polyelectrolyte forming the polyelectrolyte layer may include at least one polymer selected from the group consisting of polyallylamine hydrochloride, polydiallyldimethylammonium chloride, polyacrylic acid, poly sodium-4-styrene-sulfonate, polyethyleneimine and/or polyvinyl pyridine. The material forming the tunneling oxide layer may be silicon oxide, silicon nitride, lanthanum oxide, lanthanum silicate and/or lanthanum aluminate. [0013]According to other example embodiments, the material forming the tunneling oxide layer may be SiO.sub.2, SiO.sub.xN.sub.y, ZrO.sub.2, HfON.sub.x, ZrON.sub.x, TiO.sub.2, Ta.sub.2O.sub.5, La.sub.2O.sub.3, PrO.sub.2, HfSiO.sub.2, ZrSiO.sub.2 and/or HfSiO.sub.xN.sub.y. The nanocrystals may be arranged on the polyelectrolyte layer using a method (e.g., spin-coating, dip coating and/or drop casting). The nanocrystals may be capped with polar organic molecules having charges. The nanocrystals may be metal nano particles including Pt, Pd, Co, Cu, Mo, Ni, Fe; Group II-VI compound semiconductor nano particles including CdS, CdSe, CdTe, ZnS, ZnSe, ZnTe, HgS, HgSe, HgTe; Group III-V compound semiconductor nano particles including GaN, GaP, GaAs, InP, InAs; or PbS, PbSe, and PbTe, wherein the nanocrystals may be a metal or alloy having a size of about 10 nm or less or may be in a Core-Shell structure. The nanocrystals may be arranged as a monolayer. [0014]According to example embodiments, a memory device may include a substrate, a source region and a drain region that may be formed in the substrate and may be spaced apart from each other, a memory cell that may be formed on the surface of the substrate, connecting the source region and the drain region, and including a plurality of nanocrystals, wherein the memory cell may include a tunneling oxide layer formed on the substrate; and a control oxide layer including a plurality of nanocrystals formed on the tunneling oxide layer, and a control gate formed on the memory cell. [0015]According to example embodiments, the at least one tunneling oxide layer may include first and second tunneling oxide layers. The material forming the tunneling oxide layer may be silicon oxide, silicon nitride, lanthanum oxide, lanthanum silicate and/or lanthanum aluminate. The material forming the tunneling oxide layer may be SiO.sub.2, SiO.sub.xN.sub.y, ZrO.sub.2, HfON.sub.x, ZrON.sub.x, TiO.sub.2, Ta.sub.2O.sub.5, La.sub.2O.sub.3, PrO.sub.2, HfSiO.sub.2, ZrSiO.sub.2 and/or HfSiO.sub.xN.sub.y. The memory device may further include one kind of nanocrystals selected from the group consisting of metal nano particles including Pt, Pd, Co, Cu, Mo, Ni, Fe; Group II-VI compound semiconductor nano particles including CdS, CdSe, CdTe, ZnS, ZnSe, ZnTe, HgS, HgSe, HgTe; Group III-V group compound semiconductor nano particles including GaN, GaP, GaAs, InP, InAs and PbS, PbSe, and PbTe, wherein the nanocrystals may be a metal and/or alloy having a size of about 10 nm or less or may be in a Core-Shell structure. In the memory device, a plurality of nanocrystals included in the control oxide layer may be arranged as a monolayer. [0016]According to example embodiments, a method of operating a memory device may include grounding a source region, and applying a voltage (Vd>0) to a drain region so that electrons move from the source region to the drain region, and wherein when a gate voltage Va is greater than a drain voltage Vd, electrons move to a memory cell. The gate voltage may be a write voltage (Va=0). The method may further include applying a read voltage smaller that the gate voltage Va during writing to the drain region, wherein the gate voltage is about 0. The method may also further include applying an erase voltage to the source region to allow electrons to move to the source region, wherein the gate voltage is about 0 and the erase voltage is greater than 0. BRIEF DESCRIPTION OF THE DRAWINGS [0017]Example embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings. FIGS. 1-7 represent non-limiting, example embodiments as described herein. [0018]FIG. 1 is a diagram of a memory device according to example embodiments; [0019]FIGS. 2A-2E illustrate a method of manufacturing a memory device according to example embodiments; [0020]FIGS. 3A-3F illustrate a method of manufacturing a memory device according to example embodiments; Continue reading about Memory device and method of manufacturing the same... Full patent description for Memory device and method of manufacturing the same Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Memory device and method of manufacturing the same patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. 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