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  Memory device and method of manufacturing including deuterated oxynitride charge trapping structureUSPTO Application #: 20060192248Title: Memory device and method of manufacturing including deuterated oxynitride charge trapping structure Abstract: A method for manufacturing a charge storage stack including a bottom dielectric layer, a charge trapping structure on the bottom dielectric layer, and a top dielectric layer, each comprising silicon oxynitride, are formed using reactant gases that comprise hydrogen, where the hydrogen comprises at least 90 percent deuterium isotope. The bottom dielectric layer, charge trapping structure, and top dielectric layer each have respective relative concentrations of oxygen and nitrogen. The relative concentration of nitrogen in the charge trapping structure is high enough for the material to act as a charge trapping structure with an energy gap that is lower than the energy gaps in the bottom dielectric layer and the top dielectric layer. The presence of oxygen in the charge trapping structure reduces the number of available dangling bonding sites, and thereby reduces the number of hydrogen inclusions in the structure. (end of abstract) Agent: Macronix C/o Haynes Beffell & Wolfeld LLP - Half Moon Bay, CA, US Inventor: Szu-Yu Wang USPTO Applicaton #: 20060192248 - Class: 257324000 (USPTO) Related Patent Categories: Active Solid-state Devices (e.g., Transistors, Solid-state Diodes), Field Effect Device, Having Insulated Electrode (e.g., Mosfet, Mos Diode), Variable Threshold (e.g., Floating Gate Memory Device), Multiple Insulator Layers (e.g., Mnos Structure) The Patent Description & Claims data below is from USPTO Patent Application 20060192248. Brief Patent Description - Full Patent Description - Patent Application Claims
RELATED APPLICATION DATA [0001] The present application is a divisional of co-pending U.S. patent application Ser. No. 10/968,306 filed on 19 Oct. 2004, entitled Memory Device and Method of Manufacturing Including Deuterated Oxynitride Charge Trapping Structure. BACKGROUND OF THE INVENTION [0002] 1. Field of the Invention [0003] The present invention relates to nonvolatile memory devices and methods for manufacturing such devices. [0004] 2. Description of Related Art [0005] Electrically programmable and erasable nonvolatile memory technologies based on charge storage structures known as EEPROM and flash memory are used in a variety of modern applications. A number of memory cell structures are used for EEPROM and flash memory. As the dimensions of integrated circuits shrink, greater interest is arising for memory cell structures based on charge trapping dielectric layers, because of the scalability and simplicity of the manufacturing processes. Memory cell structures based on charge trapping dielectric layers include structures known by the industry names NROM, SONOS, and PHINES, for example. These memory cell structures store data by trapping charge in a charge trapping dielectric layer, such as silicon nitride. As negative charge is trapped, the threshold voltage of the memory cell increases. The threshold voltage of the memory cell is reduced by removing negative charge from the charge trapping layer. [0006] Conventional SONOS devices use ultra-thin bottom oxide, e.g. less than 3 nanometers, and a bias arrangement that causes direct tunneling for channel erase. Although the erase speed is fast using this technique, the charge retention is poor due to the charge leakage through ultra-thin bottom oxide. [0007] NROM devices use a relatively thick bottom oxide, e.g. greater than 3 nanometers, and typically about 5 to 9 nanometers, to prevent charge loss. Instead of direct tunneling, band-to-band tunneling induced hot hole injection BTBTHH can be used to erase the cell. However, the hot hole injection causes oxide damage, leading to charge loss in the high threshold cell and charge gain in the low threshold cell. [0008] In addition, charge trapping memory devices capture electrons in a charge trapping layer in both shallow and deep energy levels. Electrons trapped in shallow levels tend to de-trap faster than those electrons in deeper energy level traps. The shallow level electrons are a significant source of charge retention problems. In order to to keep good charge retention, deeply trapped electrons are preferred. [0009] For commercial products it is desirable for such devices to hold data for at least ten years without loss. However, leakage of trapped charge, from shallower and deeper traps both, occurs in such devices due to defects in the materials which accumulate over long use, or which are inherent in the structures. One known class of defects in charge trapping structures is hydrogen inclusions in dielectric layers and structures. The hydrogen inclusion occupies a weak bond in a silicon material, such as silicon dioxide and silicon nitride, and can dissociate from the lattice structure of the dielectric and become a charge carrier, which then can contribute to charge loss. FIG. 1 provides a graphical representation of a typical memory cell based on charge trapping structures. The memory cell comprises a terminal 10 acting as a source, a terminal 11 acting as a drain and a channel region 12 in the substrate. A bottom dielectric layer 13 overlies the channel region 12 and portions of the source and drain terminals 10, 11. A charge trapping layer 14 overlies the bottom dielectric and a top dielectric 15 overlies the charge trapping layer 14. A gate electrode comprising a polysilicon layer 16 and a silicide layer 17 lie over the top dielectric layer 15. A small region of the bottom dielectric layer 13, charge trapping layer 14 and top dielectric layer are expanded heuristically in the region 20 on the drawing. Silicon atoms are shown schematically with four lines representing the valence electrons normally available for bonding, including the three pronged lines coupled on one side of the Si symbols, with one prong on the other side. Most of the bonding sites are occupied in the top and bottom dielectrics by oxygen. However, some hydrogen atoms attach to dangling bonding sites in the lattice structure, becoming trapped hydrogen inclusions in the dielectric, illustrated by the H in a circle. In the charge trapping layer 14, most of the bonding sites are occupied by nitrogen, with some hydrogen inclusions. [0010] A number of investigators have looked at replacing hydrogen inclusions with deuterium isotopes of hydrogen, which form stronger bonds with silicon and do not dissociate and become charge carriers as easily. See for example U.S. Pat. No. 6,670,241 entitled SEMICONDUCTOR MEMORY WITH DEUTERATED MATERIALS, by Kamal et al. Kamal et al. suggests that the top and bottom oxides in an ONO charge trapping layer, as well as overlying structures such as polysilicon wordlines, and the silicon nitride charge trap, all of which contain silicon, can be "deuterated" to improve charge retention characteristics of the memory cell. (See, column 5, lines 56-61, and column 4, lines 43-52.) However, improved processes and structures are desirable which can be applied to very small devices, and achieve long retention times. SUMMARY OF THE INVENTION [0011] The present invention provides a method for manufacturing a charge storage stack with improved data retention characteristics, applicable for use in very small memory devices. The method includes the formation of a stack including a bottom dielectric layer, a charge trapping structure on the bottom dielectric layer, and a top dielectric layer. The bottom dielectric layer, the charge trapping structure, and the top dielectric layer each comprise silicon oxynitride, and are formed using reactant gases that comprise hydrogen, where the hydrogen comprises at least 90 percent deuterium isotope. The bottom dielectric layer, charge trapping structure, and top dielectric layer include hydrogen inclusions which can be described for the purposes of description as being attached to dangling silicon bonding sites that result from manufacturing processes that include reaction gases comprising hydrogen. The bottom dielectric layer, charge trapping structure, and top dielectric layer each have respective relative concentrations of oxygen and nitrogen. The relative concentrations of nitrogen in the charge trapping structure is high enough for the material to act as a charge trapping structure with an energy gap that is lower than the energy gaps in the bottom dielectric layer and the top dielectric layer. The presence of oxygen in the charge trapping structure reduces the number of available dangling bonding sites, and thereby reduces the number of hydrogen inclusions in the structure. A combination of utilizing deuterium isotope in the reactant gases and silicon oxynitride as the charge trapping structure, substantially reduces the number of hydrogen inclusions, and of those inclusions, reduces the number which are not deuterium isotope. [0012] The top and bottom dielectrics are formed in embodiments of the described process using radical oxidation processes that include in situ radical formation, such as in situ steam generation ISSG, resulting in high-quality ultrathin layers of oxide, including bottom dielectric layers less than 7 nanometers thick in some embodiments, and less than 3 nanometers thick in other embodiments. The layers of oxide can be treated with, or formed in the presence of, a nitrogen containing material. The nitrogen containing material comprises hydrogen in some embodiments, in which the hydrogen comprises at least 90 percent deuterium isotope. Use of nitrogen containing oxides in the bottom and top dielectric layers provides improved resistance to breakdown, including resistance to boron penetration which degrades device durability. The use of in situ radical oxidation processes, combined with deuterated reactant gas and nitrogen treatments in the top and bottom dielectric further enhances performance of the charge storage stack. [0013] The technology described herein provides a new memory device with improved durability and charged retention characteristics. A memory device comprises the terminal, such as a source or drain having a first conductivity type in a substrate, the region in the substrate adjacent the terminal having a second conductivity type, the bottom dielectric over portions of the terminal in the region, the charged storage structure on the bottom dielectric, and the top dielectric over the charged storage structure. As mentioned above, the bottom dielectric layer, the charge trapping structure, and the top dielectric layer each comprise silicon oxynitride, and are formed using reactant gases that comprise hydrogen, where the hydrogen comprises at least 90 percent deuterium isotope. The bottom dielectric layer, charge trapping structure, and top dielectric layer include hydrogen inclusions which can be described for the purposes of description as being attached to dangling silicon bonding sites that result from manufacturing processes that include reaction gases comprising hydrogen. The bottom dielectric layer, charge trapping structure, and top dielectric layer each have respective relative concentrations of oxygen and nitrogen. The relative concentrations of nitrogen in the charge trapping structure is high enough for the material to act as a charge trapping structure with an energy gap that is lower at the interfaces between the layers in the stack, than the energy gaps at the interfaces in the bottom dielectric layer and in the top dielectric layer. [0014] Other aspects and advantages of the present invention can be seen on review of the drawings, the detailed description and the claims, which follow. BRIEF DESCRIPTION OF THE DRAWINGS [0015] FIG. 1 is a simplified diagram of a prior art memory device with hydrogen inclusions. [0016] FIG. 2 is a diagram of a memory device including a stack of silicon oxynitride layers with hydrogen inclusions that comprise deuterium isotope, configured as a charge storage device. [0017] FIG. 3 is a flowchart of a representative process for manufacturing a memory device like that shown in FIG. 2. [0018] FIG. 4 is a flowchart of another representative process for manufacturing a memory device like that shown in FIG. 2. DETAILED DESCRIPTION [0019] A detailed description of embodiments of the present invention is provided with reference to the FIGS. 2, 3 and 4. Continue reading... Full patent description for Memory device and method of manufacturing including deuterated oxynitride charge trapping structure Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Memory device and method of manufacturing including deuterated oxynitride charge trapping structure patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. 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