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Memory device and method of manufacturing a memory deviceRelated Patent Categories: Semiconductor Device Manufacturing: Process, Making Field Effect Device Having Pair Of Active Regions Separated By Gate Structure By Formation Or Alteration Of Semiconductive Active Regions, Having Insulated Gate (e.g., Igfet, Misfet, Mosfet, Etc.)Memory device and method of manufacturing a memory device description/claimsThe Patent Description & Claims data below is from USPTO Patent Application 20070037334, Memory device and method of manufacturing a memory device. Brief Patent Description - Full Patent Description - Patent Application Claims
BACKGROUND [0001] The invention relates to a memory device having an array of memory cells such as DRAM (Dynamic Random Access Memory) cells, as well as to a method of manufacturing such a memory device. [0002] Memory cells of a dynamic random access memory (DRAM) generally include a storage capacitor for storing an electrical charge that represents an information to be stored and an access transistor which is connected with a storage capacitor. The access transistor includes a first and a second source/drain region, a channel connecting the first and the second source/drain region as well as a gate electrode controlling an electrical current flow between the first and the second source/drain region. The transistor usually is at least partially formed in the semiconductor substrate. The gate electrode forms part of the word line and is electrically insulated from the channel by a gate dielectric. By addressing the access transistor via a corresponding word line, the information stored in the storage capacitor is read out to a corresponding bit line. [0003] In the currently used DRAM memory cells, the storage capacitor can be implemented as a trench capacitor in which the two capacitor electrodes are disposed in a trench that extends in the substrate in a direction perpendicular to the substrate surface. [0004] In one implementation of the DRAM memory cell, the electrical charge is stored in a stacked capacitor, which is formed above the surface of the substrate. [0005] FIG. 28 illustrates an exemplary plan view of a memory device, having a memory cell array II and a peripheral portion I. A boundary region III is formed between the memory cell array II and the peripheral portion I. The memory cell array II includes a plurality of memory cells 330, each of the memory cells have a storage capacitor 24 and an access transistor 30. The storage capacitor includes a first and a second capacitor electrode 17, 19, the first capacitor electrode 17 being connected with a first source/drain region 31 of the access transistor. The channel 33 is formed between the first and the second source/drain region 31, 32 and a gate electrode 34 controls the conductivity of the channel 33. The gate electrode 34 is insulated from the channel 33 by a gate insulating layer 35. By addressing the address transistor 30 via the corresponding word line 310, the information stored in the storage capacitor is read out to a corresponding bit line 320. The layout illustrated in FIG. 28 corresponds to the so-called folded bit line layout. However, as is to be clearly understood, the present invention is applicable to any kind of memory cell array layouts. [0006] The support portion I refers to a portion at the edge of the memory cell array in which support circuits such as decoders, sense amplifiers 340 and word line drivers 350 for activating a word line 310 are located. Generally, the peripheral portion of a memory device includes circuitry for addressing memory cells and for sensing and processing the signals received from the individual memory cells. Usually, the peripheral portion is formed in the same semiconductor substrate as the individual memory cells. In addition, the boundary region is as well formed in the same semiconductor substrate. Hence, it is highly desirable to have a manufacturing process by which the components of the memory cell array and the peripheral portion can be formed simultaneously. [0007] In particular, if the storage capacitor of the memory cell is implemented as a stacked capacitor extending above the semiconductor substrate surface, a problem arises that the whole substrate surface is covered by a thick sacrificial layer which is removed during the processing of the stacked capacitor. After completion of the capacitor, a second deposition step of a dielectric layer has to be made in order to provide an insulation for the following metal layer. [0008] A further problem arises, that during the processing of the peripheral portion a contact for contacting the peripheral portion has to be formed by etching a contact hole through a thick layer (3 .mu.m) of an insulating material. [0009] U.S. Pat. No. 5,895,239 discloses a method of forming a memory device in which bit lines in the array portion are formed simultaneously with landing plugs in the peripheral portion. In particular, according to this patent, the landing plugs are formed at a level of the first wiring layer. SUMMARY [0010] According to one embodiment of the present invention, a method of forming a memory device includes providing a semiconductor substrate having a surface and providing an array portion having an array of access transistors, each of said access transistors having a first and a second source/drain region. A channel is disposed between said first and second source/drain region and a gate electrode which is electrically insulated from said channel and adapted to control the conductivity of said channel, each of said access transistors being at least partially formed in said semiconductor substrate. The method also includes providing a peripheral portion including peripheral circuitry, said peripheral portion being at least partially formed in said semiconductor substrate. A substrate portion between said peripheral portion and said array of access transistors defines a boundary region. The method includes providing a plurality of array contact pads connected with said first source/drain regions, said array contact pads being electrically insulated from each other. The method includes providing a plurality of storage capacitors including providing a sacrificial layer covering said array contact pads, defining openings in said sacrificial layer, each of said openings being in contact with a corresponding one of said array contact pads, defining an array separation trench in the sacrificial layer at said boundary region, said array separation trench having a surface, providing a storage electrode of a conductive material in each of said openings, respectively, so that each of said storage electrodes is in contact with a corresponding one of said array contact pads, covering the surface of said array separation trench with a first masking material which is different from the material of said sacrificial layer, masking the peripheral portion with a layer of a second masking material which is different from the material of the sacrificial layer, and removing the sacrificial layer from the array portion while maintaining the sacrificial layer in the peripheral portion, providing a storage dielectric on said storage electrode and a counter electrode on said storage dielectric in the array portion thereby completing the plurality of storage capacitors. [0011] One embodiment of the present invention provides a method of forming a memory device that makes use of a sacrificial layer for the definition of the storage capacitors. This sacrificial layer is removed only from the array and maintained in the peripheral portion. In one embodiment, the sacrificial layer is removed from the array portion after providing the storage electrodes. BRIEF DESCRIPTION OF THE DRAWINGS [0012] The accompanying drawings are included to provide a further understanding of the present invention and are incorporated in and constitute a part of this specification. The drawings illustrate the embodiments of the present invention and together with the description serve to explain the principles of the invention. Other embodiments of the present invention and many of the intended advantages of the present invention will be readily appreciated as they become better understood by reference to the following detailed description. The elements of the drawings are not necessarily to scale relative to each other. Like reference numerals designate corresponding similar parts. [0013] FIGS. 1 to 6 illustrate a method of forming a memory device according to one embodiment of the present invention. [0014] FIGS. 7 to 24 illustrate steps of the method of forming a memory device according to one embodiment of the present invention. [0015] FIG. 25 illustrates a cross-sectional view of a memory device according to one embodiment of the present invention. [0016] FIG. 26 illustrates a further embodiment of the present invention. [0017] FIG. 27 illustrates a plan view on the memory cell array including the boundary region which can be manufactured by the method of one embodiment of the present invention. [0018] FIG. 28 illustrates a schematic view of the memory device of the present invention. DETAILED DESCRIPTION [0019] In the following Detailed Description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced. In this regard, directional terminology, such as "top," "bottom," "front," "back," "leading," "trailing," etc., is used with reference to the orientation of the Figure(s) being described. Because components of embodiments of the present invention can be positioned in a number of different orientations, the directional terminology is used for purposes of illustration and is in no way limiting. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention. The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims. [0020] One embodiment provides a method of forming a memory device with a sacrificial layer. The sacrificial layer in one case is made of silicon dioxide. The etching step for etching the sacrificial layer stops at an array separation trench which laterally protects the peripheral portion from being etched. In one embodiment, the openings and the array separation trench are defined by one etching step of etching the sacrificial layer. In one case, the array separation trench and the openings are formed by the same process steps. Further, in one case a first separation layer, for example made of silicon nitride, is formed on the surface of the array contact pads. The first separation layer is made of a material which is different from the material of the sacrificial layer. Thereby, an etch stop layer is provided on the surface of the array contact pads. Continue reading about Memory device and method of manufacturing a memory device... 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