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  Memory controllerUSPTO Application #: 20080052447Title: Memory controller Abstract: A memory controller for writing data in a first semiconductor memory including a plurality of memory cells having series-connected current paths and charge storage layers includes a host interface which configured to be receivable of first data from a host apparatus, a second semiconductor memory which temporarily holds second data, and an arithmetic unit which generates the second data in accordance with the state of the first semiconductor memory, temporarily holds the second data in the second semiconductor memory, and writes the first and second data in the first semiconductor memory. When writing the second data, the arithmetic unit does not select a word line adjacent to a select gate line, and selects a word line not adjacent to the select gate line. (end of abstract)
Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C. - Alexandria, VA, US Inventors: Hiroshi SUKEGAWA, Takeshi Nakano USPTO Applicaton #: 20080052447 - Class: 711103 (USPTO) The Patent Description & Claims data below is from USPTO Patent Application 20080052447. Brief Patent Description - Full Patent Description - Patent Application Claims
CROSS-REFERENCE TO RELATED APPLICATIONS [0001]This application is based upon and claims the benefit of priority from prior Japanese Patent Application No. 2006-194804, filed Jul. 14, 2006, the entire contents of which are incorporated herein by reference. BACKGROUND OF THE INVENTION [0002]1. Field of the Invention [0003]The present invention relates to a memory controller, e.g., a memory controller for controlling the operation of a nonvolatile semiconductor memory chip. [0004]2. Description of the Related Art [0005]With the recent rapid spread of digital cameras and portable audio players, demands for large-capacity nonvolatile semiconductor memories are increasing, and NAND flash memories (to be also simply referred to as flash memories hereinafter) are widely used as the nonvolatile semiconductor memories. [0006]In the NAND flash memory, data is erased from a plurality of memory cells at once. This erase unit will be called a memory block hereinafter. The memory block includes a plurality of NAND cells. Each NAND cell has a selection transistor ST1 having a drain connected to a bit line, a selection transistor ST2 having a source connected to a source line, and a plurality of memory cell transistors MT having current paths connected in series between the source of the selection transistor ST1 and the drain of the selection transistor ST2. [0007]In the conventional NAND flash memory described above, data is written by selecting a certain word line. This technique is described in, e.g., "Jpn. Pat. Appln. KOKAI Publication No. 2005-285184" or "SmartMedia.TM. (registered trademark) Physical Format Specification Ver 1.21, issued by SSFDC Forum Technical Meeting, May 19, 1999". However, this technique has the problem that the reliability of the system deteriorates due to the loss of important data. BRIEF SUMMARY OF THE INVENTION [0008]A memory controller according to the first aspect of the present invention which writes data in a first semiconductor memory including a plurality of memory cells, a first selection transistor, a second selection transistor, a first select gate line, a second select gate line and a plurality of word lines, the plurality of memory cells having current paths connected in series between a source of the first selection transistor and a drain of the second selection transistor, each of the plurality of memory cells having a control gate and a charge storage layer, the first and second select gate lines respectively connected to gates of the first and second selection transistors, and the plurality of word lines respectively connected to the control gates, the memory controller comprising a host interface which is configured to be connectable to a host apparatus and to be receivable of first data from the host apparatus, a second semiconductor memory which temporarily holds second data, and an arithmetic unit which generates the second data in accordance with a state of the first semiconductor memory, temporarily holds the second data in the second semiconductor memory, and writes, in the first semiconductor memory, the first data from the host interface and the second data held in the second semiconductor memory, wherein when writing the second data, the arithmetic unit does not select the word lines adjacent to the first select gate line and the second select gate line, and selects the word line not adjacent to the first select gate line and the second select gate line. [0009]A memory controller according to the second aspect of the present invention which writes data in a first semiconductor memory including a plurality of memory cells, a first selection transistor, a second selection transistor, a first select gate line, a second select gate line and a plurality of word lines, the plurality of memory cells having current paths connected in series between a source of the first selection transistor and a drain of the second selection transistor, each of the plurality of memory cells having a control gate and a charge storage layer and being configured to hold data having at least two bits, the first and second select gate lines respectively connected to gates of the first and second selection transistors, and the plurality of word lines respectively connected to the control gates, the memory controller comprising a host interface which is configured to be connectable to a host apparatus and to be receivable of first data from the host apparatus, a second semiconductor memory which temporarily holds second data, and an arithmetic unit which generates the second data in accordance with a state of the first semiconductor memory, temporarily holds the second data in the second semiconductor memory, and writes, in the first semiconductor memory, the first data from the host interface and the second data held in the second semiconductor memory, wherein when writing the second data, the arithmetic unit writes one-bit data in the memory cells connected to the word lines adjacent to the first select gate line and the second select gate line, and writes the data having not less than two bits in the memory cell connected to the word line not adjacent to the first select gate line and the second select gate line. BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING [0010]FIG. 1 is a block diagram of a memory system according to the first embodiment of the present invention; [0011]FIG. 2 is a view showing the assignment of signals to signal pins in a memory card according to the first embodiment of the present invention; [0012]FIG. 3 is a block diagram of a card controller of the memory card according to the first embodiment of the present invention; [0013]FIG. 4 is a block diagram of a flash memory according to the first embodiment of the present invention; [0014]FIG. 5 is a circuit diagram of a memory block of the flash memory according to the first embodiment of the present invention; [0015]FIG. 6 is a conceptual view of system information of the card controller according to the first embodiment of the present invention; [0016]FIG. 7 is a flowchart showing the processing of a write operation of the card controller according to the first embodiment of the present invention; [0017]FIG. 8 is a circuit diagram of the memory block of the flash memory according to the first embodiment of the present invention, which shows the way the system information is written; [0018]FIG. 9 is a graph showing the threshold distribution of a flash memory according to the second embodiment of the present invention; [0019]FIG. 10 is a flowchart showing the processing of a write operation of a card controller according to the second embodiment of the present invention; [0020]FIG. 11 is a circuit diagram of a memory block of the flash memory according to the second embodiment of the present invention, which shows the way the system information is written; Continue reading... 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The shutdown object may be ... ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. Start now! - Receive info on patent apps like Memory controller or other areas of interest. ### Previous Patent Application: Logical super block mapping for nand flash memory Next Patent Application: Method for page random write and read in blocks of flash memory Industry Class: Electrical computers and digital processing systems: memory ### FreshPatents.com Support Thank you for viewing the Memory controller patent info. IP-related news and info Results in 5.26031 seconds Other interesting Feshpatents.com categories: Daimler Chrysler , DirecTV , Exxonmobil Chemical Company , Goodyear , Intel , Kyocera Wireless , |
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