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Memory control method and memory controllerRelated Patent Categories: Error Detection/correction And Fault Detection/recovery, Pulse Or Data Error Handling, Digital Logic TestingMemory control method and memory controller description/claimsThe Patent Description & Claims data below is from USPTO Patent Application 20070043985, Memory control method and memory controller. Brief Patent Description - Full Patent Description - Patent Application Claims
CROSS REFERENCE TO RELATED APPLICATION [0001] This application claims the priority of Application No. 2005-217581, filed on Jul. 27, 2005 in Japan, the subject matter of which is incorporated herein by reference. TECHNICAL FIELD OF THE INVENTION [0002] The present invention relates to a pre-read control of an address for when a transfer frequency with respect to a memory controller is irregular. BACKGROUND OF THE INVENTION [0003] In a read access, to improve performance, a memory controller which controls a main memory may predict the next address from a transfer type and a current address of a system bus connected to a CPU, a master, and the like. [0004] In this case, if the transfer frequency is known (fixed) beforehand, an extra access can be prevented, but if the transfer frequency is uncertain, the extra access cannot be prevented. Therefore, extra power consumption increases. [0005] In Japanese Unexamined Patent Publication No. 2004-318252, it is disclosed to perform pre-reading in read control of an SDRAM. [Patent Document 1] Japanese Unexamined Patent Publication No. 2004-318252 [0006] However, in the invention disclosed in the above document, the pre-read data is only reused as effective data as in a cache memory to improve the performance, and an extra access preventing effect cannot be obtained. OBJECTS OF THE INVENTION [0007] Accordingly, an object of the present invention is to provide a memory control method and a memory controller, which can prevent an extra access when the transfer frequency is uncertain. [0008] Additional objects, advantages and novel features of the present invention will be set forth in part in the description that follows, and in part will become apparent to those skilled in the art upon examination of the following or may be learned by practice of the invention. The objects and advantages of the invention may be realized and attained by means of the instrumentalities and combinations particularly pointed out in the appended claims. SUMMARY OF THE INVENTION [0009] According to a first aspect of the present invention, a memory access control method is a method of controlling continuous transfers from a master connected to a system bus to a memory controller, which comprises steps of: retaining a transfer frequency of continuous transfers performed with respect to the memory controller; predicting the transfer frequency for this time based on the retained past transfer frequency, when the transfer frequency with respect to the memory controller is irregular; and accessing a memory connected to the memory controller first, based on the predicted transfer frequency. [0010] According to a second aspect of the present invention a memory controller controls access to an external memory from a system bus. The memory controller comprises: a transfer frequency retaining circuit which retains a transfer frequency of continuous transfers performed with respect to the memory controller; and a transfer frequency predicting circuit which predicts the transfer frequency for this time based on the retained past transfer frequency, when the transfer frequency with respect to the memory controller is irregular. The memory controller accesses the memory first, based on the transfer frequency obtained by the transfer frequency predicting circuit. [0011] As described above, according to the present invention, when the continuous access to the memory controller (the number of burst transfers) is uncertain, the transfer frequency of irregular continuous access currently performed is predicted based on a history of the past transfer frequency, thereby enabling reduction of useless accesses. As a result, an increase in power consumption can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS [0012] FIG. 1 is a block diagram showing a schematic configuration of a bus system to which the present invention is applied. [0013] FIG. 2 is a block diagram showing an overall configuration of a memory controller according to a first embodiment of the present invention. [0014] FIG. 3 is a block diagram showing a configuration of a control signal generation block, being a main part of the memory controller according to the first embodiment. [0015] FIG. 4 is a timing chart showing an operation in the first embodiment. [0016] FIG. 5 is a block diagram showing an overall configuration of the memory controller according to a second embodiment of the present invention. [0017] FIG. 6 is a block diagram showing a configuration of a "lastcnt" generation block, being the main part of the memory controller according to the second embodiment. [0018] FIG. 7 is a block diagram showing an overall configuration of the memory controller according to a third embodiment of the present invention. Continue reading about Memory control method and memory controller... Full patent description for Memory control method and memory controller Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Memory control method and memory controller patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. 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