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Memory cell arraysRelated Patent Categories: Active Solid-state Devices (e.g., Transistors, Solid-state Diodes), Gate Arrays, Having Specific Type Of Active Device (e.g., Cmos), Particular Layout Of Complementary Fets With Regard To Each OtherMemory cell arrays description/claimsThe Patent Description & Claims data below is from USPTO Patent Application 20060208282, Memory cell arrays. Brief Patent Description - Full Patent Description - Patent Application Claims
CROSS REFERENCE TO RELATED APPLICATIONS [0001] This application is a continuation of U.S. Ser. No. 10/059,727, filed Jan. 29, 2002, which is a continuation of U.S. Ser. No. 09/340,983, filed Jun. 28, 1999, now U.S. Pat. No. 6,410,948, which is a continuation-in-part of U.S. Ser. No. 08/918,657, filed Aug. 22, 1997, now U.S. Pat. No. 6,025,221, all of which are hereby incorporated by reference. BACKGROUND [0002] The invention relates to memory cell arrays. [0003] In a continuing effort to reduce the size of memory devices, different memory cell array topologies have been proposed. FIG. 24 illustrates a portion of a typical memory cell array in a semiconductor memory device (such as a dynamic random access memory) that includes parallel word lines 100 running along one direction and bit lines 102 running generally perpendicularly to the word lines 100. Bit line contacts 104 electrically connect the bit lines 102 and the associated cell structure, generally indicated as 106. [0004] The size of each cell is typically described in terms of its feature size (F). The feature size is based on the width of the electrically conductive lines (i.e., the word lines and bit lines), referred to as L, and the width of the isolation space between the conductive lines, referred to as S. The sum of L and S is the minimum pitch of the memory device. The feature size (F) is half the minimum pitch, or half the sum of L and S, that is, F = L + S 2 . ( Eq . .times. 1 ) [0005] In the cell configuration shown in FIG. 24, the width of each cell along the word line direction is 2F while the width along the bit line direction is 4F. This results in a cell size of 8F.sup.2 (2F.times.4F). To reduce the size of memory devices, reduced memory cell topologies have been proposed, including 6F.sup.2 cells. However, with reduced cell sizes, several issues need to be addressed, including capacitor size, ease of contact to cells, and alignment between the contacts and cells. [0006] In addition, processing of semiconductor devices typically involves many steps in which layers of material are formed over a substrate and subsequently patterned into a desired feature or structure. Typical features or structures include conductive lines (e.g., word lines, bit lines) and contact openings. Each time a patterning or etching step is conducted, certain risks arise which can jeopardize the integrity of a wafer being processed. For example, a mask misalignment error can cause a subsequent etch to undesirably etch into wafer or substrate structure which can cause catastrophic failure. Accordingly, a need exists to reduce the number of processing steps utilized in the formation of integrated circuitry. SUMMARY [0007] In general, in one embodiment, a memory device includes, bit lines and continuous active area lines extending generally in a first direction and intersecting at slanted portions. [0008] Other features and advantages will become apparent from the drawings and from the following claims. BRIEF DESCRIPTION OF THE DRAWINGS [0009] FIGS. 1A and 1B are schematic diagrams of memory arrays. [0010] FIGS. 2A and 2B are enlarged, top views of a semiconductor wafer fragment in accordance with embodiments of the invention. [0011] FIG. 3 is a cross sectional view of the FIG. 2A wafer fragment at one processing step taken along line 12-12 in FIG. 2A. [0012] FIG. 4 corresponds to FIG. 3 but shows the wafer fragment at another processing step. [0013] FIG. 5 corresponds to FIG. 3 but shows the wafer fragment at another processing step. [0014] FIG. 6 corresponds to FIG. 3 but shows the wafer fragment at another processing step. [0015] FIG. 7 corresponds to FIG. 3 but shows the wafer fragment at another processing step. [0016] FIG. 8 corresponds to FIG. 3 but shows the wafer fragment at another processing step. [0017] FIG. 9 corresponds to FIG. 3 but shows the wafer fragment at another processing step. [0018] FIG. 10 corresponds to FIG. 3 but shows the wafer fragment at another processing step. [0019] FIG. 11 corresponds to FIG. 3 but shows the wafer fragment at another processing step. [0020] FIG. 12 corresponds to FIG. 3 but shows the wafer fragment at another processing step. Continue reading about Memory cell arrays... Full patent description for Memory cell arrays Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Memory cell arrays patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. 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