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  Memory buffers for merging local data from memory modulesUSPTO Application #: 20060195631Title: Memory buffers for merging local data from memory modules Abstract: An integrated circuit to serialize local data and selectively merge it with serialized feed-through data into a serial data stream output that includes a parallel-in-serial-out (PISO) shift register, a multiplexer, and a transmitter. The PISO shift register serializes parallel data on a local data bus into serialized local data. The multiplexer selectively merges serialized local data and feed-through data into a serial data stream. The transmitter drives the serial data stream onto a serial data link. In another embodiment of the invention, a method for a memory module includes receiving an input serial data stream; merging local frames of data and feed-through frames of data together into an output serial data stream in response to a merge enable signal; and transmitting the output serial data stream on a northbound data output to a next memory module or a memory controller. Other embodiments of the invention are disclosed and claimed. (end of abstract) Agent: Blakely Sokoloff Taylor & Zafman - Los Angeles, CA, US Inventor: Ramasubramanian Rajamani USPTO Applicaton #: 20060195631 - Class: 710051000 (USPTO) Related Patent Categories: Electrical Computers And Digital Data Processing Systems: Input/output, Input/output Data Processing, Input/output Access Regulation, Accessing Via A Multiplexer The Patent Description & Claims data below is from USPTO Patent Application 20060195631. Brief Patent Description - Full Patent Description - Patent Application Claims
FIELD [0001] Embodiments of the invention relate generally to memory, and specifically to merging data from a memory buffer onto serial data channels. BACKGROUND INFORMATION [0002] In memory circuits there is typically a memory read latency that is the time period it takes for valid data to be read out of a memory circuit. A memory write latency is typically also required that is the time period to hold valid data for a memory circuit to write the data into memory. The memory read latency and the memory write latency may sometimes be buffered from a processor by a cache memory. However, there are occasions when the desired data is not found in the cache memory. In those cases, a processor may need to then read or write data with the memory circuits. Thus, the respective memory read latency or memory write latency may be experienced by the processor. If memory circuits differ, the memory read latencies and memory write latency may be inconsistent from one memory circuit to the next. In which case, the memory read latency and memory write latency experienced by a processor will differ. [0003] Previously, memory modules were plugged into a mother or host printed circuit board and coupled in parallel to a parallel data bus over which parallel data could be read from and written into memory. The parallel data bus had parallel data bit lines that were synchronized together to transfer one or more data bytes or words of data at a time. The parallel data bit lines are typically routed over a distance on a printed circuit board (PCB) from one memory module socket to another. This introduces a first parasitic capacitive load. As the memory modules are plugged into a memory socket, an additional parasitic capacitive load is introduced onto the parallel data bits lines of the parallel data bus. As there may be a number of memory modules plugged in, the additional parasitic capacitive load may be significant and bog down high frequency memory circuits. [0004] One memory module is typically addressed by an address on address lines at a time. The one addressed memory module, typically writes data onto the parallel data bus at a time. Other memory modules typically have to wait to write data onto the parallel data bus in order to avoid collisions. [0005] While parallel data bit lines may speed data flow in certain instances, a parallel data bus in a memory may slow the read and write access of data between a memory circuit and a processor. BRIEF DESCRIPTION OF THE DRAWINGS [0006] FIG. 1A illustrates a block diagram of a typical computer system in which embodiments of the invention may be utilized. [0007] FIG. 1B illustrates a block diagram of a client-server system in which embodiments of the invention may be utilized. [0008] FIG. 2A illustrates a block diagram of a central processing unit in which embodiments of the invention may be utilized. [0009] FIG. 2B illustrates a block diagram of another central processing unit in which embodiments of the invention may be utilized. [0010] FIG. 3 illustrates a simplified block diagram of a buffered memory controller to couple data into and out of banks of buffered memory modules. [0011] FIG. 4 illustrates a block diagram of a buffered memory module including a buffer that may merge data with feed through data. [0012] FIG. 5 illustrates a detailed block diagram of a buffered memory controller coupling to a bank of buffered memory modules. [0013] FIG. 6 (FIGS. 6-1 and 6-2) illustrates a functional block diagram of a buffer of a buffered memory module. [0014] FIG. 7A illustrates a simplified block diagram of the data merge logic including lanes of data merge logic slices coupled to transmitters. [0015] FIG. 7B illustrates a schematic diagram of a data merge logic slice for one lane of serial data. [0016] FIG. 8 illustrates a timing diagram of signals for a data merge logic slice functioning in a twelve bit mode. [0017] FIG. 9 illustrates a timing diagram of signals for a data merge logic slice functioning in a six-bit mode. [0018] FIG. 10 illustrates a flow chart for the initialization, training, and functioning of the buffer in merging local data and feed through data together into a serial data stream output. DETAILED DESCRIPTION [0019] In the following detailed description of embodiments of the invention, numerous specific details are set forth in order to provide a thorough understanding of the invention. However, it will be obvious to one skilled in the art that the embodiments of the invention may be practiced without these specific details. In other instances well known methods, procedures, components, and circuits have not been described in detail so as not to unnecessarily obscure aspects of the embodiments of the invention. [0020] Generally the embodiments of the invention provide a data merge feature, referred to as a Northbound Data Merge (NBDM), that replaces parts of the data on a high speed link with its own data, on the fly. That is, the embodiments of the invention replace part of the incoming serial data traffic (e.g., "idle packets or frames") over a serial data link with its local data, without having internal core logic process (e.g., serial-to-parallel conversion, assemblage into frames, and depacketize/deinterleave data) the incoming serial data traffic to determine where to insert the local data and retransmit the incoming data traffic with the local data inserted therein. Continue reading... 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