| Membrane-based chip tooling -> Monitor Keywords |
|
|
  Membrane-based chip toolingUSPTO Application #: 20060278331Title: Membrane-based chip tooling Abstract: A method for use with multiple chips, each respectively having a bonding surface including electrical contacts and a surface on a side opposite the bonding surface involves bringing a hardenable material located on a body into contact with the multiple chips, hardening the hardenable material so as to constrain at least a portion of each of the multiple chips, moving the multiple chips from a first location to a second location, applying a force to the body such that the hardened, hardenable material will uniformly transfer a vertical force, applied to the body, to the chips so as to bring, under pressure, a bonding surface of each individual chip into contact with a bonding surface of an element to which the individual chips will be bonded, at the second location, without causing damage to the individual chips, element, or bonding surface. (end of abstract) Agent: Morgan & Finnegan, L.L.P. - New York, NY, US Inventors: Roger Dugas, John Trezza USPTO Applicaton #: 20060278331 - Class: 156230000 (USPTO) Related Patent Categories: Adhesive Bonding And Miscellaneous Chemical Manufacture, Methods, Surface Bonding And/or Assembly Therefor, Direct Contact Transfer Of Adhered Lamina From Carrier To Base The Patent Description & Claims data below is from USPTO Patent Application 20060278331. Brief Patent Description - Full Patent Description - Patent Application Claims
FIELD OF THE INVENTION [0001] The present invention relates to semiconductors and, more particularly, to electrical connections for such devices. BACKGROUND [0002] Making electrical contacts that extend all the way through an electronic chip (by creating electrically conductive vias) is difficult. Doing so with precision or controlled repeatability, let alone in volume is nearly impossible unless one or more of the following is the case: a) the vias are very shallow, i.e. significantly less than 100 microns in depth, b) the via width is large, or c) the vias are separated by large distances, i.e. many times the via width. The difficulty is compounded when the vias are close enough for signal cross-talk to occur, or if the chip through which the via passes has a charge, because the conductor in the via can not be allowed act as a short, nor can it carry a charge different from the charge of the pertinent portion of the chip. In addition, conventional processes, to the extent they exist, are unsuitable for use with formed integrated circuit (IC) chips (i.e. containing active semiconductor devices) and increase cost because those processes can damage the chips and thereby reduce the ultimate yield. Adding further to the above difficulties is the need to be concerned with capacitance and resistance problems when the material the via passes through has a charge or when the frequencies of the signals to be carried through the vias are very high, for example, in excess of about 0.3 GHz. [0003] Indeed, there are numerous problems that are extant in the semiconductor art including: use of large, non-scaleable packaging; assembly costs don't scale like semiconductors; chip cost is proportional to area, and the highest performance processes are the most expensive, but only fraction of chip area actually requires high-performance processes; current processes are limited in voltage and other technologies; chip designers are limited to one process and one material for design; large, high power pad drivers are needed for chip-to-chip (through package) connections; even small changes or correction of trivial design errors require fabrication of one or more new masks for a whole new chip; making whole new chips requires millions of dollars in mask costs alone; individual chips are difficult and complicated to test and combinations of chips are even more difficult to test prior to complete packaging. [0004] Accordingly, there is a significant need in the art for technology that can address one or more of the above problems. SUMMARY OF THE INVENTION [0005] We have developed a process that facilitates forming chip to chip electrical connections with vias that pass through a wafer, a preformed third-party chip, or a doped semiconductor substrate. Aspects described herein aid in the approach and represent improvements in the general field of joining of chips to each other. [0006] One aspect involves a method for use with multiple chips, each respectively having a bonding surface including electrical contacts and a surface on a side opposite the bonding surface involves bringing a hardenable material located on a body into contact with the multiple chips, hardening the hardenable material so as to constrain at least a portion of each of the multiple chips, moving the multiple chips from a first location to a second location, applying a force to the body such that the hardened, hardenable material will uniformly transfer a vertical force, applied to the body, to the chips so as to bring, under pressure, a bonding surface of each individual chip into contact with a bonding surface of an element to which the individual chips will be bonded, at the second location, without causing damage to the individual chips or bonding surface. [0007] Another aspect involves bonding each of the individual chips to the element. [0008] Yet another aspect involves an apparatus for use with multiple chips, each respectively having a bonding surface including electrical contacts and a surface on a side opposite the bonding surface, the apparatus having a body, a material on a surface of the body that can be applied to the body in a viscous liquid or gel form and hardened into a hardened state, the material being in a hardened state and enveloping and restraining at least a portion of each of the multiple chips in such a manner so as to allow a uniform vertical force to be applied to the body from a side opposite the material of sufficient magnitude so as to bring the bonding surface on each of the at least two chips into contact with a respective corresponding bonding surface of an element to which the chips will be bonded without causing damage to the respective individual chips, the bonding surface, or the element. [0009] The advantages and features described herein are a few of the many advantages and features available from representative embodiments and are presented only to assist in understanding the invention. It should be understood that they are not to be considered limitations on the invention as defined by the claims, or limitations on equivalents to the claims. For instance, some of these advantages are mutually contradictory, in that they cannot be simultaneously present in a single embodiment. Similarly, some advantages are applicable to one aspect of the invention, and inapplicable to others. Thus, this summary of features and advantages should not be considered dispositive in determining equivalence. Additional features and advantages of the invention will become apparent in the following description, from the drawings, and from the claims. BRIEF DESCRIPTION OF THE DRAWINGS [0010] FIG. 1 is a simplified representation a side view of a portion of a chip containing multiple active electronic devices; [0011] FIG. 2 is a top view of the upper surface of the specified area of FIG. 1; [0012] FIG. 3 shows a simplified cutaway view of the portion of FIG. 1; [0013] FIG. 4 is a top view of the upper surface of the specified area of FIG. 1 following creation of the trench shown in side view in FIG. 3; [0014] FIG. 5 shows a simplified cutaway view of the portion of FIG. 1 as a result of continued processing; [0015] FIG. 6 is a top view of the upper surface of the specified area of FIG. 1 following the filling of the trench with electrically insulating material shown in side view in FIG. 5; [0016] FIG. 7 shows a simplified cutaway view of the portion of FIG. 1 as a result of continued processing; [0017] FIG. 8 is a top view of the upper surface of the specified area 124 of FIG. 1 following the creation of the via trench; [0018] FIG. 9 shows a simplified cutaway view of the portion of FIG. 1 as a result of continued processing; [0019] FIG. 10 is a top view of the upper surface of the specified area of FIG. 1 following metalization of the via trench; [0020] FIG. 11 shows a simplified cutaway view of the portion of FIG. 1 as a result of continued optional processing; Continue reading... Full patent description for Membrane-based chip tooling Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Membrane-based chip tooling patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. Start now! - Receive info on patent apps like Membrane-based chip tooling or other areas of interest. ### Previous Patent Application: Chemically modified melamine resin for use in sublimation dye imaging Next Patent Application: Method of manufacturing a flexible display device Industry Class: Adhesive bonding and miscellaneous chemical manufacture ### FreshPatents.com Support Thank you for viewing the Membrane-based chip tooling patent info. IP-related news and info Results in 10.2379 seconds Other interesting Feshpatents.com categories: Software: Finance , AI , Databases , Development , Document , Navigation , Error |
||
