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Martine Penilla & Gencarella, LLP patentsThe following is a sampling of recent Martine Penilla & Gencarella, LLP patent applications (USPTO Patent Application #, Patent Title) sorted by month.
February 2011 - Martine Penilla & Gencarella, LLP patents
20110039410 - Apparatus and method for substrate electroless plating
20110041107 - Identifying semiconductor system specification violations
20110030733 - Post sputter wash process module
20110032574 - Image output system for outputting image based on information of number of dots to be formed in predetermined area
20110035722 - Method for specifying stateful, transaction-oriented systems for flexible mapping to structurally configurable in-memory processing semiconductor device
20110023424 - Horse bit
20110023779 - Variable volume plasma processing chamber and associated methods
20110024045 - Apparatus and method for controlling plasma potential
20110024046 - Apparatus and method for controlling plasma potential
20110024889 - Package architecture
20110025359 - Bond and probe pad distribution
January 2011 - Martine Penilla & Gencarella, LLP patents
20110017605 - Proximity processing using controlled batch volume with an integrated proximity head
20110011335 - Electroless plating method and apparatus
20110014361 - Electroless deposition solutions and process control
20110008916 - Proximity head heating method and apparatus
December 2010 - Martine Penilla & Gencarella, LLP patents
20100329232 - Methods and systems for communication protocol for distributed asset management
20100331226 - Damage-free high efficiency particle removal clean
20100319726 - Substrate preparation using megasonic coupling fluid meniscus
20100313443 - Substrate proximity drying using in-situ local heating of substrate
20100313917 - Method of particle contaminant removal
20100313918 - Apparatus for cleaning contaminants from substrate
20100313965 - Locking fire hydrant
20100315064 - Methods of and apparatus for measuring and controlling wafer potential in pulsed rf bias processing
20100317556 - Two-phase substrate cleaning material
20100308957 - Device for controlling an actuator
20100309604 - Method and apparatus for chuck thermal calibration
20100300492 - Method and apparatus for physical confinement of a liquid meniscus over a semiconductor wafer
20100303298 - Selective sound source listening in conjunction with computer interactive processing
20100303353 - Output image data generating device and method of generating output image data
20100304132 - Controlled vapor deposition of multilayered coatings adhered by an oxide layer
20100304868 - Multi-positional three-dimensional controller
20100306402 - Addition of supplemental multimedia content and interactive capability at the client
20100306719 - Integrated circuit cell library with cell-level process compensation technique (pct) application and associated methods
November 2010 - Martine Penilla & Gencarella, LLP patents
20100293810 - Apparatus and method for drying a substrate
20100294742 - Modifications to surface topography of proximity head
20100288311 - Multi-stage substrate cleaning method and apparatus
20100290197 - Modular data center and associated methods
20100290872 - Substrate container storage system
20100290873 - Integrated systems for interfacing with substrate container storage systems
20100290887 - Soft-sided containers and systems and methods for using soft-sided containers
20100283065 - Led device with a light extracting rough structure and manufacturing methods thereof
20100283575 - Mlock device and associated methods
20100284030 - Color conversion apparatus, color conversion method, color change program and recording medium
20100285472 - Primers and probes for detection of high risk group geno-type human papillomavirus dna, a qualitative assay method of the same dna using them and a qualitative assay kit of the same dna
20100285879 - Base station for position location
20100285883 - Base station movement detection and compensation
20100287272 - Method for structuring a self-organized content distribution overlay network for a peer-to-peer network
20100287518 - Cell circuit and layout with linear finfet structures
20100277201 - Embedded digital ip strip chip
20100277202 - Circuitry and layouts for xor and xnor logic
20100280932 - System and method for managing and deploying functional services to a vehicle client
20100281314 - Smart fields
October 2010 - Martine Penilla & Gencarella, LLP patents
20100269285 - Apparatus and system for cleaning substrate
20100269365 - System and method for alternating fluid flow
20100271513 - Selection of decorative picture suitable for input picture
20100273553 - System for converting television commercials into interactive networked video games
20100264432 - Light emitting device with high color rendering index and high luminescence efficiency
20100265359 - Output image adjustment of image data
20100258142 - Apparatus and method for using a viscoelastic cleaning material to remove particles on a substrate
20100258879 - Channelized gate level cross-coupled transistor device with cross-coupled transistor gate electrode connections made using linear first interconnect level above gate electrode level
20100261527 - Methods and systems for enabling control of artificial intelligence game characters
20100252889 - Linear gate level cross-coupled transistor device with contiguous p-type diffusion regions and contiguous n-type diffusion regions
20100252890 - Linear gate level cross-coupled transistor device with non-overlapping pmos transistors and non-overlapping nmos transistors relative to direction of gate electrodes
20100252891 - Linear gate level cross-coupled transistor device with equal width pmos transistors and equal width nmos transistors
20100252892 - Channelized gate level cross-coupled transistor device with different width pmos transistors and different width nmos transistors
20100252893 - Channelized gate level cross-coupled transistor device with cross-coupled transistors defined on three gate electrode tracks with crossing gate electrode connections
20100252896 - Methods, structures, and designs for self-aligning local interconnects used in integrated circuits
20100257150 - Query identification and normalization for web search
September 2010 - Martine Penilla & Gencarella, LLP patents
20100248033 - Lithium batteries with nano-composite positive electrode material
20100237426 - Linear gate level cross-coupled transistor device with cross-coupled transistor gate electrode connections made using linear first interconnect level above gate electrode level
20100237427 - Channelized gate level cross-coupled transistor device with contiguous p-type diffusion regions and contiguous n-type diffusion regions
20100237428 - Channelized gate level cross-coupled transistor device with non-overlapping pmos transistors and overlapping nmos transistors relative to direction of gate electrodes
20100237429 - Channelized gate level cross-coupled transistor device with non-overlapping pmos transistors and non-overlapping nmos transistors relative to direction of gate electrodes
20100237430 - Channelized gate level cross-coupled transistor device with equal width pmos transistors and equal width nmos transistors
20100239176 - Image arrangement for electronic album
20100239179 - Generation of image quality adjustment information and image quality adjustment with image quality adjustment information
20100239767 - Apparatus for applying a plating solution for electroless deposition
20100241692 - Methods and systems for dynamically adjusting update rates in multi-player network gaming
20100229890 - Method of particle contaminant removal
20100230243 - Wafer carrier drive apparatus and method for operating the same
20100232703 - Image processing apparatus, image processing method, and program product thereof
August 2010 - Martine Penilla & Gencarella, LLP patents
20100206340 - Method for removing contamination from a substrate and for making a cleaning solution
20100208946 - Specifying flesh area on image
20100210808 - Method for preparing polysilazane solution with reducing ammonia substitution of si-h bond
20100211731 - Hard disk drive with attached solid state drive cache
20100211903 - User interface for wafer data analysis and visualization
20100200045 - Solar power system and method of manufacturing and deployment
20100205060 - Context-sensitive route generation system
20100205373 - Smart sd card and method of accessing the same
July 2010 - Martine Penilla & Gencarella, LLP patents
20100186180 - Support structure for multiple workpiece support rollers
20100187615 - Linear gate level cross-coupled transistor device with direct electrical connection of cross-coupled transistors to common diffusion node
20100187616 - Linear gate level cross-coupled transistor device with overlapping pmos transistors and overlapping nmos transistors relative to direction of gate electrodes
20100187617 - Linear gate level cross-coupled transistor device with non-overlapping pmos transistors and overlapping nmos transistors relative to direction of gate electrodes
20100187618 - Linear gate level cross-coupled transistor device with overlapping pmos transistors and non-overlapping nmos transistors relative to direction of gate electrodes
20100187619 - Linear gate level cross-coupled transistor device with different width pmos transistors and different width nmos transistors
20100187620 - Linear gate level cross-coupled transistor device with connection between cross-coupled transistor gate electrodes made utilizing interconnect level other than gate electrode level
20100187621 - Linear gate level cross-coupled transistor device with constant gate electrode pitch
20100187622 - Linear gate level cross-coupled transistor device with complimentary pairs of cross-coupled transistors defined by physically separate gate electrodes within gate electrode level
20100187623 - Linear gate level cross-coupled transistor device with cross-coupled transistors defined on two gate electrode tracks with crossing gate electrode connections
20100187624 - Linear gate level cross-coupled transistor device with cross-coupled transistors defined on three gate electrode tracks with crossing gate electrode connections
20100187625 - Linear gate level cross-coupled transistor device with cross-coupled transistors defined on four gate electrode tracks with crossing gate electrode connections
20100187626 - Channelized gate level cross-coupled transistor device with direct electrical connection of cross-coupled transistors to common diffusion node
20100187627 - Channelized gate level cross-coupled transistor device with overlapping pmos transistors and overlapping nmos transistors relative to direction of gate electrodes
20100187628 - Channelized gate level cross-coupled transistor device with overlapping pmos transistors and non-overlapping nmos transistors relative to direction of gate electrodes
20100187630 - Channelized gate level cross-coupled transistor device with connection between cross-coupled transistor gate electrodes made utilizing interconnect level other than gate electrode level
20100187631 - Channelized gate level cross-coupled transistor device with constant gate electrode pitch
20100187632 - Channelized gate level cross-coupled transistor device with complimentary pairs of cross-coupled transistors defined by physically separate gate electrodes within gate electrode level
20100187633 - Channelized gate level cross-coupled transistor device with cross-coupled transistors defined on two gate electrode tracks with crossing gate electrode connections
20100187634 - Channelized gate level cross-coupled transistor device with cross-coupled transistors defined on four gate electrode tracks with crossing gate electrode connections
20100181644 - Ic package with capacitors disposed on an interposal layer
20100182620 - Image processing device and image processing method
20100186054 - Method for transmitting near video on demand (nvod) using catch and rest (car) and sub-channels
20100176846 - Differential hybrid circuit
20100177541 - Voltage-sourced hvdc system with modulation function
20100170539 - Reduction of entrance and exit marks left by a substrate-processing meniscus
20100170803 - Method and apparatus for plating semiconductor wafers
20100171071 - Lithium iron phosphate having oxygen vacancy and doped in the position of fe and method of quick solid phase sintering for the same
20100173710 - Pattern codes used for interactive control of computer applications
20100164584 - Timing generator
20100167127 - Lithium iron phosphate battery electrode and method for manufacturing the same
20100169846 - Methods for gate-length biasing using annotation data
20100169847 - Standard cells having transistors annotated for gate-length biasing
20100167551 - Dual path gas distribution device
June 2010 - Martine Penilla & Gencarella, LLP patents
20100157691 - Dual port pld embedded memory block to support read-before-write in one clock cycle
20100148375 - Vertically tapered transmission line for optimal signal transition in high-speed multi-layer ball grid array packages
20100148826 - Differential comparator with skew compensation function and test apparatus using the same
20100150474 - Generation of high-resolution images based on multiple low-resolution images
20100150695 - Method and system for centering wafer on chuck
20100139694 - Cleaning compound and method and system for using the cleaning compound
20100140089 - Flexible ph sensors and ph sensing systems using the same
20100144436 - Control device for communicating visual information
20100134114 - Apparatus and method for three-pole type measuring specific soil resistance measurement for distribution grounding
May 2010 - Martine Penilla & Gencarella, LLP patents
20100126528 - Confinement of foam delivered by a proximity head
20100126847 - Apparatus and method for controlling plasma density profile
20100129695 - Molding material for fuel cell separator
20100125136 - Porphyrin-based photosensitizer dyes for dye-sensitized solar cells
20100116290 - Composition and application of a two-phase contaminant removal medium
20100119170 - Image compression by comparison to large database
20100120647 - Composition of a cleaning material for particle removal
20100108093 - Acoustic assisted single wafer wet clean for semiconductor wafer process
20100108652 - System method and apparatus for dry-in, dry-out, low defect laser dicing using proximity technology
20100109103 - Mems package
20100109675 - Method to digitize analog signals in a system utilizing dynamic analog test multiplexer for diagnostics
20100111651 - Tactile wafer lifter and methods for operating the same
20100115507 - Methods for securely distributing computer software products
April 2010 - Martine Penilla & Gencarella, LLP patents
20100102976 - System and method for monitoring vibration of power transformer
20100104059 - Renormalization method of excore detector
20100105475 - Determining location and movement of ball-attached controller
20100105480 - Spherical ended controller with configurable modes
20100107133 - Method for increasing cell uniformity in an integrated circuit by adjusting cell inputs to design process
20100096087 - Apparatus for aligning electrodes in a process chamber to protect an exclusion area within an edge environ of a wafer
20100096671 - Cell of semiconductor device having gate electrode conductive structures formed from rectangular shaped gate electrode layout features and at least eight transistors
20100097476 - Method and apparatus for optimizing capture device settings through depth information
20100098266 - Multi-channel audio device
20100100221 - Expert knowledge methods and systems for data analysis
20100085445 - Adjustment for output image of image data
20100078207 - Universal bump array structure
20100079152 - Methods for measuring dielectric properties of parts
20100079200 - Process/design methodology to enable high performance logic and analog circuits using a single process
20100082177 - System and method for controlling multiple facts
March 2010 - Martine Penilla & Gencarella, LLP patents
20100071730 - Methods for atomic layer deposition (ald) using a proximity meniscus
20100071734 - Hydraulic drive type partial inter-tube lancing system for cleaning steam generator in nuclear power plant
20100075034 - Controlled deposition of silicon-containing coatings adhered by an oxide layer
20100067030 - Image color adjustment
20100059088 - Method and apparatus for removing contamination from substrate
20100060336 - Semiconductor circuit
20100060662 - Visual identifiers for virtual world avatars
20100061627 - Determination of main object on image and improvement of image quality according to main object
20100052651 - Pulse width measurement circuit
20100054141 - Method and system for mbs over mmr network using dynamic modification of mcs level
20100054350 - Modulation method and modulator using pulse edge shift
20100054370 - Demodulation method and demodulator of pulse-edge shifted pulse
20100056277 - Methods for directing pointing detection conveyed by user when interfacing with a computer program
February 2010 - Martine Penilla & Gencarella, LLP patents
20100043822 - Removing bubbles from a fluid flowing down through a plenum
20100045249 - Voltage regulator for write/read assist circuit
20100038032 - System and method for critical dimension reduction and pitch reduction
20100042727 - Method and system for managing a peer of a peer-to-peer network to search for available resources
20100042964 - Reuse of circuit labels in subcircuit recognition
20100032721 - Semiconductor device portion having sub-193 nanometers -sized gate electrode conductive structures formed from linear shaped gate electrode layout features defined with minimum end-to-end spacing and having equal number of pmos and nmos transistors
20100032722 - Semiconductor device portion having gate electrode conductive structures formed from linear shaped gate electrode layout features defined with minimum end-to-end spacing and having at least eight transistors
20100032723 - Semiconductor device portion having sub-wavelength-sized gate electrode conductive structures formed from linear shaped gate electrode layout features defined with minimum end-to-end spacing and having at least eight transistors
20100032724 - Cell of semiconductor device having sub-193 nanometers-sized gate electrode conductive structures formed from rectangular shaped gate electrode layout features and equal number of pmos and nmos transistors
20100032726 - Semiconductor device portion having sub-193 nanometers -sized gate electrode conductive structures formed from linear shaped gate electrode layout features defined along at least four gate electrode tracks with minimum end-to-end spacing and having corres
20100033427 - Computer image and audio processing of intensity and input devices for interfacing with a computer program
20100034621 - End effector to substrate offset detection and correction
20100037194 - Layout of cell of semiconductor device having linear shaped gate electrode layout features defined with minimum end-to-end spacing and having equal number of pmos and nmos transistors
20100037195 - Layout of cell of semiconductor device having linear shaped gate electrode layout features defined with minimum end-to-end spacing and having equal number of pmos and nmos transistors and having corresponding p-type and n-type diffusion regions separated
20100024842 - Generator for foam to clean substrate
20100025731 - Cell of semiconductor device having gate electrode conductive structures formed from linear shaped gate electrode layout features defined with minimum end-to-end spacing and equal number of pmos and nmos transistors
20100025732 - Cell of semiconductor device having sub-wavelength-sized gate electrode conductive structures formed from linear shaped gate electrode layout features defined with minimum end-to-end spacing and at least eight transistors
20100025733 - Cell of semiconductor device having sub-193 nanometers-sized gate electrode conductive structures formed from linear shaped gate electrode layout features defined with minimum end-to-end spacing and at least eight transistors
20100025734 - Cell of semiconductor device having sub-wavelength-sized gate electrode conductive structures formed from linear shaped gate electrode layout features defined with minimum end-to-end spacing and equal number of pmos and nmos transistors
20100025735 - Cell of semiconductor device having sub-193 nanometers-sized gate electrode conductive structures formed from linear shaped gate electrode layout features defined with minimum end-to-end spacing and equal number of pmos and nmos transistors
20100025736 - Cell of semiconductor device having gate electrode conductive structures formed from linear shaped gate electrode layout features defined with minimum end-to-end spacing and at least eight transistors
20100028111 - Variable-size load port and method for operating the same
20100031211 - Methods for controlling microloading variation in semiconductor wafer layout and fabrication
January 2010 - Martine Penilla & Gencarella, LLP patents
20100018253 - Crystallized glass article having patterns and method of producing the same
20100018553 - Method and apparatus for surface treatment of semiconductor substrates using sequential chemical applications
20100019280 - Cell of semiconductor device having gate electrode conductive structures formed from rectangular shaped gate electrode layout features defined along at least four gate electrode tracks
20100019281 - Cell of semiconductor device having sub-wavelength-sized gate electrode conductive structures formed from rectangular shaped gate electrode layout features defined along at least four gate electrode tracks
20100019282 - Cell of semiconductor device having sub-193 nanometers-sized gate electrode conductive structures formed from rectangular shaped gate electrode layout features defined along at least four gate electrode tracks
20100019283 - Cell of semiconductor device having sub-wavelength-sized gate electrode conductive structures formed from rectangular shaped gate electrode layout features and equal number of pmos and nmos transistors
20100019284 - Cell of semiconductor device having sub-wavelength-sized gate electrode conductive structures formed from rectangular shaped gate electrode layout features and at least eight transistors
20100019285 - Cell of semiconductor device having sub-193 nanometers-sized gate electrode conductive structures formed from rectangular shaped gate electrode layout features and at least eight transistors
20100019286 - Cell of semiconductor device having gate electrode conductive structures formed from linear shaped gate electrode layout features defined along at least four gate electrode tracks with minimum end-to-end spacing
20100019287 - Cell of semiconductor device having sub-193 nanometers-sized gate electrode conductive structures formed from linear shaped gate electrode layout features defined along at least four gate electrode tracks with minimum end-to-end spacing
20100019288 - Cell of semiconductor device having sub-wavelength-sized gate electrode conductive structures formed from linear shaped gate electrode layout features defined along at least four gate electrode tracks with minimum end-to-end spacing
20100023906 - Layout of cell of semiconductor device having linear shaped gate electrode layout features defined along at least four gate electrode tracks with minimum end-to-end spacing
20100023907 - Layout of cell of semiconductor device having linear shaped gate electrode layout features defined along at least four gate electrode tracks with minimum end-to-end spacing and having corresponding p-type and n-type diffusion regions separated by central
20100023908 - Layout of cell of semiconductor device having linear shaped gate electrode layout features defined with minimum end-to-end spacing and having at least eight transistors and having corresponding p-type and n-type diffusion regions separated by central inac
20100023911 - Layout of cell of semiconductor device having linear shaped gate electrode layout features defined with minimum end-to-end spacing and having at least eight transistors
20100012649 - Irradiation facility of radiant heat
20100012732 - Installing a patch in a smart card module
20100012981 - Semiconductor device portion having gate electrode conductive structures formed from linear shaped gate electrode layout features defined along at least four gate electrode tracks with minimum end-to-end spacing and having corresponding non-symmetric diff
20100012982 - Semiconductor device portion having sub-wavelength-sized gate electrode conductive structures formed from linear shaped gate electrode layout features defined along at least four gate electrode tracks with minimum end-to-end spacing and having correspondi
20100012983 - Semiconductor device portion having gate electrode conductive structures formed from linear shaped gate electrode layout features defined with minimum end-to-end spacing and having equal number of pmos and nmos transistors
20100012984 - Semiconductor device portion having sub-wavelength-sized gate electrode conductive structures formed from linear shaped gate electrode layout features defined with minimum end-to-end spacing and having equal number of pmos and nmos transistors
20100012985 - Semiconductor device portion having sub-193 nanometers -sized gate electrode conductive structures formed from linear shaped gate electrode layout features defined with minimum end-to-end spacing and having at least eight transistors
20100012986 - Cell of semiconductor device having gate electrode conductive structures formed from rectangular shaped gate electrode layout features and equal number of pmos and nmos transistors
20100015731 - Method of low-k dielectric film repair
20100016202 - Materials and systems for advanced substrate cleaning
20100017766 - Semiconductor device layout including cell layout having restricted gate electrode level layout with linear shaped gate electrode layout features defined with minimum end-to-end spacing and at least eight transistors
20100017767 - Layout of cell of semiconductor device having rectangular shaped gate electrode layout features defined along at least four gate electrode tracks
20100017768 - Layout of cell of semiconductor device having rectangular shaped gate electrode layout features defined along at least four gate electrode tracks with corresponding p-type and n-type diffusion regions separated by central inactive region
20100017769 - Layout of cell of semiconductor device having rectangular shaped gate electrode layout features and equal number of pmos and nmos transistors
20100017770 - Layout of cell of semiconductor device having rectangular shaped gate electrode layout features and equal number of pmos and nmos transistors with corresponding p-type and n-type diffusion regions separated by central inactive region
20100017771 - Layout of cell of semiconductor device having rectangular shaped gate electrode layout features and at least eight transistors
20100017772 - Layout of cell of semiconductor device having rectangular shaped gate electrode layout features and at least eight transistors with corresponding p-type and n-type diffusion regions separated by central inactive region
20100006897 - Semiconductor device layout having restricted layout region including rectangular shaped gate electrode layout features and equal number of pmos and nmos transistors
20100006898 - Semiconductor device layout including cell layout having restricted gate electrode level layout with rectangular shaped gate electrode layout features and at least eight transistors
20100006899 - Semiconductor device portion having gate electrode conductive structures formed from rectangular shaped gate electrode layout features and having equal number of pmos and nmos transistors
20100006900 - Semiconductor device portion having sub-wavelength-sized gate electrode conductive structures formed from rectangular shaped gate electrode layout features and having equal number of pmos and nmos transistors
20100006901 - Semiconductor device portion having gate electrode conductive structures formed from rectangular shaped gate electrode layout features defined along at least four gate electrode tracks and having corresponding non-symmetric diffusion regions
20100006902 - Semiconductor device portion having sub-wavelength-sized gate electrode conductive structures formed from rectangular shaped gate electrode layout features defined along at least four gate electrode tracks and having corresponding non-symmetric diffusion
20100006903 - Semiconductor device portion having sub-193 nanometers-sized gate electrode conductive structures formed from rectangular shaped gate electrode layout features defined along at least four gate electrode tracks and having corresponding non-symmetric diffus
20100006947 - Semiconductor device portion having sub-wavelength-sized gate electrode conductive structures formed from rectangular shaped gate electrode layout features and having at least eight transistors
20100006948 - Semiconductor device portion having sub-193 nanometers -sized gate electrode conductive structures formed from rectangular shaped gate electrode layout features and having at least eight transistors
20100006950 - Semiconductor device portion having gate electrode conductive structures formed from rectangular shaped gate electrode layout features and having at least eight transistors
20100006951 - Semiconductor device portion having sub-193 nanometers -sized gate electrode conductive structures formed from rectangular shaped gate electrode layout features and having equal number of pmos and nmos transistors
20100006986 - Semiconductor device layout including cell layout having restricted gate electrode level layout with rectangular shaped gate electrode layout features defined along at least four gate electrode tracks with corresponding non-symmetric diffusion regions
20100007366 - Test equipment and semiconductor device
20100008155 - Structurally field-configurable semiconductor array for in-memory processing of stateful, transaction-oriented systems
20100008171 - Read assist circuit of sram with low standby current
20100008518 - Methods for processing audio input received at an input device
20100011267 - Multi-strobe circuit
20100011327 - Semiconductor device layout having restricted layout region including rectangular shaped gate electrode layout features and at least eight transistors
20100011328 - Semiconductor device layout including cell layout having restricted gate electrode level layout with linear shaped gate electrode layout features defined with minimum end-to-end spacing and equal number of pmos and nmos transistors
20100011329 - Semiconductor device layout including cell layout having restricted gate electrode level layout with rectangular shaped gate electrode layout features and equal number of pmos and nmos transistors
20100011330 - Semiconductor device layout having restricted layout region including linear shaped gate electrode layout features defined along at least four gate electrode tracks with minimum end-to-end spacing with corresponding non-symmetric diffusion regions
20100011331 - Semiconductor device layout including cell layout having restricted gate electrode level layout with linear shaped gate electrode layout features defined along at least four gate electrode tracks with minimum end-to-end spacing with corresponding non-symm
20100011332 - Semiconductor device layout having restricted layout region including linear shaped gate electrode layout features defined with minimum end-to-end spacing and equal number of pmos and nmos transistors
20100011333 - Semiconductor device layout having restricted layout region including linear shaped gate electrode layout features defined with minimum end-to-end spacing and at least eight transistors
20100001077 - Card-shaped data carrier
20100001321 - Semiconductor device layout having restricted layout region including rectangular shaped gate electrode layout features defined along at least four gate electrode tracks with corresponding non-symmetric diffusion regions
20100001410 - Flip chip overmold package
20100003507 - Multi-layer polyimide film and method of manufacturing the same
December 2009 - Martine Penilla & Gencarella, LLP patents
20090320749 - Apparatus for integrated surface treatment and deposition for copper interconnect
20090320884 - Controls of ambient environment during wafer drying using proximity head
20090320942 - Single substrate processing head for particle removal using low viscosity fluid
20090321250 - Apparatus for plating semiconductor wafers
20090321624 - Ion trap, multiple electrode system and electrode for mass spectrometric analysis
20090327854 - Analysis of database performance reports for graphical presentation of summary results
20090327903 - System and method for network topology and flow visualization
20090327985 - Highly threaded static timer
20090316727 - Real-time optimization of tx fir filter for high-speed data communication
20090319250 - System, method and apparatus for sensitivity based fast power grid simulation with variable time step
20090308410 - Method and material for cleaning a substrate
20090308413 - Apparatus and system for cleaning a substrate
20090309240 - Return loss techniques in wirebond packages for high-speed data communications
20090310643 - Methods and apparatus for thin metal film thickness measurement
20090303349 - Image processing apparatus and method of image processing
20090303819 - Write and read assist circuit for sram with power recycling
20090304914 - Self assembled monolayer for improving adhesion between copper and barrier layer
20090294981 - Methods for defining and using co-optimized nanopatterns for integrated circuit design and apparatus implementing same
20090296139 - Selection of image data for output
20090298590 - Expandable control device via hardware attachment
20090300574 - Methods for defining and utilizing sub-resolution features in linear topology
20090300575 - Optimizing layout of irregular structures in regular layout context
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This listing is an abstract for educational and research purposes is only meant as a recent sample of applications filed, not a comprehensive history. Freshpatents.com is not affiliated or associated with Martine Penilla & Gencarella, LLP in any way and there may be associated servicemarks. This data is also published to the public by the USPTO and available for free on their website. Note that there may be alternative spellings for Martine Penilla & Gencarella, LLP with additional patents listed. Browse our Agent directory for other possible listings.
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