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Manufacturing method for an integrated semiconductor structure and corresponding integrated semiconductor structureRelated Patent Categories: Active Solid-state Devices (e.g., Transistors, Solid-state Diodes), Field Effect Device, Having Insulated Electrode (e.g., Mosfet, Mos Diode), Insulated Gate Field Effect Transistor In Integrated Circuit, Complementary Insulated Gate Field Effect TransistorsManufacturing method for an integrated semiconductor structure and corresponding integrated semiconductor structure description/claimsThe Patent Description & Claims data below is from USPTO Patent Application 20070187774, Manufacturing method for an integrated semiconductor structure and corresponding integrated semiconductor structure. Brief Patent Description - Full Patent Description - Patent Application Claims
[0001] This is a continuation of U.S. application Ser. No. 11/183,224, which was filed Jul. 14, 2005 and is now U.S. Pat. No. 7,202,535, issued Apr. 10, 2007. TECHNICAL FIELD [0002] The present invention relates to a manufacturing method for an integrated semiconductor structure and to a corresponding integrated semiconductor structure. BACKGROUND [0003] U.S. Pat. No. 5,843,812 describes a manufacturing process of a p-MOSFET having a polysilicon gate wherein a BF.sub.2 ion implantation is performed into the polysilicon gate in order to achieve a more stable threshold voltage. [0004] Although in principle applicable to arbitrary integrated semiconductor structures, the following invention and the underlying problems will be explained with respect to integrated memory circuits in silicon technology. [0005] To improve the speed of the periphery devices, the device length as well as a gate oxide thickness have to be scaled down. Below a certain thickness of 2 nm, the gate leakage is very important and increases exponentially. High-k dielectrics are supposed to improve the gate oxide problem. However, the integration of the high-k dielectric together with a N.sup.+ polysilicon gate is very difficult due to the fermi-level pinning. [0006] Also, gate polysilicon depletion is becoming a limiting factor for on-current of small gate-length transistors with a thin gate dielectric having a thickness of less than about 2 nm. The gate poly-depletion effect usually contributes to a 7-10.times.10.sup.-10 m (.ANG.) increase of the overall effective oxide thickness of the gate dielectric for logic devices. The gate polysilicon depletion is even more severe for p-MOSFETs in DRAM support devices due to the higher boron deactivation during DRAM processing. [0007] Metal gates which are free from poly-depletion effects have been anticipated for replacement of polysilicon gates. However, issues such as a process compatibility, device reliability and difficulties in integrating dual work-function metal gates for both p- and n-MOSFETs have hindered the introduction of metal gates. Though p-MOSFETs with an N.sup.+ polysilicon gate are also free from polysilicon depletion effect, the threshold voltage will be too high for any practical application due to the improper work-function of the N.sup.+ polysilicon. SUMMARY OF THE INVENTION [0008] The object of the present invention is to provide an improved manufacturing method for an integrated semiconductor structure and a corresponding integrated semiconductor structure where the Fermi-level of the p-MOSFET may be properly adjusted. [0009] The basic idea underlying the present invention is to enhance p-MOSFET performance by eliminating the gate polysilicon depletion while maintaining the appropriate threshold voltage. An N.sup.+ polysilicon gate is used as gate electrode since it is free from gate polysilicon depletion for p-MOSFETs. Moreover, a thin interfacial high-k dielectric layer, preferably an Al.sub.xO.sub.y layer, between the N.sup.+ polysilicon gate and the gate dielectric is introduced in the p-MOSFET, only. This interfacial high-k dielectric layer is chosen such that it has strong Fermi-level pinning effects on the N.sup.+ gate polysilicon. As a consequence, the effective work-function for the N.sup.+ polysilicon is adjusted to a value close to that of a corresponding P.sup.+ polysilicon gate. Hence, the threshold voltage of the p-MOSFET can still be controlled in an acceptable range. [0010] Already a very thin Al.sub.xO.sub.y layer (monolayer or several monolayers) results in an insignificant increase of the overall gate dielectric effective thickness due to its relatively high dielectric constant of about 7 to 10. [0011] Moreover, there is a good process compatibility with current Si processing compared with using metal gates. The dual work-function concept is without restrictions of the thermal budget due to boron penetration. [0012] Two general approaches are proposed for the formation of the thin high-k dielectric interfacial layer. [0013] The first approach is to deposit the high-k interfacial dielectric layer on top of the gate dielectric layer and to remove the high-k dielectric layer on top of the n-MOSFET regions by selective wet chemistry. [0014] The other approach is to implant appropriate metal irons into p-MOSFET N.sup.+ polysilicon gate areas after the patterning of the areas. Then, a thermal treatment is performed such that metal irons diffuse to the interface between the N.sup.+ polysilicon and the gate dielectric where the metal irons will react with gate dielectric (SiO.sub.2, SiO.sub.xN.sub.y or a different high-k oxide) and form the desired thin interfacial high-k dielectric layer. [0015] According to a preferred embodiment the step of forming a gate structure on the first and second transistor region includes: forming a first dielectric layer in the first and second transistor region; forming the interfacial dielectric layer in the first and second transistor region above the first dielectric layer; masking the interfacial dielectric layer in the second transistor region; removing the interfacial dielectric layer in the first transistor region; and forming the gate layer in the first and second transistor region. [0016] According to another preferred embodiment the step of forming a gate structure on the first and second transistor region includes: forming a first dielectric layer in the first and second transistor region; forming the gate layer in the first and second transistor region; performing an Al ion implantation into the second transistor region; performing a heat treatment for forming the interfacial dielectric layer in second transistor region above the first dielectric layer. [0017] According to another preferred embodiment the semiconductor substrate is provided having first, second and third transistor regions, the first transistor region being a n-MOSFET region, second transistor region being a p-MOSFET region and the third transistor region being a memory array MOSFET, and wherein at least one second dielectric layer is formed simultaneously in all of the first, second and third transistor regions. [0018] According to another preferred embodiment the second dielectric layer is a high-k dielectric layer made of HfO or HfSiO or HfSiON. [0019] According to another preferred embodiment the interfacial dielectric layer is made of a high-k material such as Al.sub.xO.sub.y, Al.sub.2O.sub.3 or HfAl.sub.xO.sub.y or any material in combination with Al.sub.2O.sub.3 that forms the Al.sub.2O.sub.3 containing interface on the gate layer. [0020] According to another preferred embodiment the gate layer in the first and second transistor regions is made of the same material and electrically connected thereby. [0021] According to another preferred embodiment the gate layer in the first and second transistor regions is made of a different material and electrically connected by a gate contact layer. Continue reading about Manufacturing method for an integrated semiconductor structure and corresponding integrated semiconductor structure... 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