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Lsi Logic Corporation patentsThe following is a sampling of recent Lsi Logic Corporation patent applications (USPTO Patent Application #, Patent Title) sorted by month.
July 2008 - Lsi Logic Corporation patents
20080172542 - Hierarchy of a structure of a volume
20080162683 - Unified management of a hardware interface framework
June 2008 - Lsi Logic Corporation patents
20080148034 - Method and apparatus for booting independent operating systems in a multi-processor core integrated circuit
20080133713 - Reliable and efficient data transfer over serial port
20080133831 - System and method of volume group creation based on an automatic drive selection scheme
August 2007 - Lsi Logic Corporation patents
20070188607 - Detection of moving interlaced text for film mode decision
20070188662 - Progressive video detection with aggregated block sads
20070190784 - Dielectric barrier layer for increasing electromigration lifetimes in copper interconnect structures
20070192639 - Apparatus and methods for power management and spin-up in a storage system
20070183491 - Context adaptive binary arithmetic decoding for high definition video
20070186198 - Generation of an extracted timing model file
20070176645 - Active current cancellation for high performance video clamps
20070178692 - Multi-step process for forming a barrier film for use in copper layer formation
20070179745 - Failure analysis and testing of semi-conductor devices using intelligent software on automated test equipment (ate)
20070180014 - Sparce-redundant fixed point arithmetic modules
July 2007 - Lsi Logic Corporation patents
20070163993 - Planarization with reduced dishing
20070164451 - Power configuration method for structured asics
20070168701 - Storing raid configuration data within a bios image
20070169009 - Method and system for outputting a sequence of commands and data described by a flowchart
20070162636 - System and method for implementing a storage protocol with initiator controlled data transfer
20070162764 - Peer-to-peer license tracking and control
20070162804 - Method of generating test patterns to efficiently screen inline resistance delay defects in complex asics
20070162886 - Customizable development and demonstration platform for structured asics
20070152151 - Method and sample for radiation microscopy including a particle beam channel formed in the sample source
20070153013 - Hybrid multiple bit-depth video processing architecture
20070154107 - Adaptive video enhancement gain control
20070155160 - Method and apparatus for redirecting void diffusion away from vias in an integrated circuit design
20070156360 - Simultaneous display of eye diagram and jitter profile during device characterization
20070156914 - Applying a transfer function to a signal for determining compliance to a specification
20070157056 - Method and apparatus for detecting defects in integrated circuit die from stimulation of statistical outlier signatures
20070157143 - System for avoiding false path pessimism in estimating net delay for an integrated circuit design
20070157145 - Method and end cell library for avoiding substrate noise in an integrated circuit
20070157152 - Method and computer program product for detecting potential failures in an integrated circuit design after optical proximity correction
June 2007 - Lsi Logic Corporation patents
20070145413 - Isolated power domain core regions in platform asics
20070147010 - Drive slot shutters for drive enclosures
20070150627 - Endian mapping engine, method of endian mapping and a processing system employing the engine and the method
20070138973 - Electrostatic discharge series protection
20070139031 - Method for simulating resistor characteristics at high electric fields
20070139065 - Testing high frequency signals on a trace
20070139552 - Unified approach to film mode detection
20070140074 - Media type detection using a lock indicator
20070140477 - Memory encryption for digital video
20070143541 - Methods and structure for improved migration of raid logical volumes
20070143725 - Automation of tie cell insertion, optimization and replacement by scan flip-flops to increase fault coverage
20070143771 - Using prml read channel adc for blank/defect and ripple detection
20070132083 - Semiconductor package having increased resistance to electrostatic discharge
20070133364 - Method and apparatus for positioning beam spot on recording medium
20070136023 - Method of using automated test equipment to screen for leakage inducing defects after calibration to intrinsic leakage
20070136503 - Systems for implementing sdram controllers, and buses adapted to include advanced high performance bus features
20070136521 - Mitigating performance degradation caused by a sata drive attached to a sas domain
20070136641 - Unified memory architecture for recording applications
20070125999 - Configurable power segmentation using a nanotube structure
20070126619 - Integrated cmos temperature sensor and analog to digital converter
20070127573 - Hierarchical motion estimation for images with varying horizontal and/or vertical dimensions
20070130486 - Timing constraints methodology for enabling clock reconvergence pessimism removal in extracted timing models
May 2007 - Lsi Logic Corporation patents
20070121001 - Accurate motion detection for the combination of motion adaptive and motion compensation de-interlacing applications
20070121013 - Method and/or apparatus for cross-color and cross-luminance suppression using shimmer detection
20070121262 - Bias for electrostatic discharge protection
20070122922 - Platform asic reliability
20070123024 - Eliminate imc cracking in post wirebonded dies: macro level stress reduction by modifying dielectric/metal film stack in be layers during cu/low-k processing
20070124407 - Systems and method for simple scale-out storage clusters
20070124628 - Methods of memory bitmap verification for finished product
20070124716 - Method for generalizing design attributes in a design capture environment
20070114613 - Programmable nanotube interconnect
20070114644 - Scaling of functional assignments in packages
20070114667 - Alternate pad structures/passivation inegration schemes to reduce or eliminate imc cracking in post wire bonded dies during cu/low-k beol processing
20070115600 - Apparatus and methods for improved circuit protection from eos conditions during both powered off and powered on states
20070115792 - Differential push pull gain method and/or apparatus to reduce the effects on rotational eccentricity
20070118716 - Method of partioning storage in systems with both single and virtual target interfaces
20070109448 - Noise adaptive 3d composite noise reduction
20070109937 - Write based power adaptive control system
20070109976 - Dynamic peer application discovery
20070110086 - Multi-mode management of a serial communication link
20070110206 - Low jitter and/or fast lock-in clock recovery circuit
20070112544 - Dynamic on-chip logic analysis
20070112937 - Storage system for pervasive and mobile content
20070102812 - Reduction of macro level stresses in copper/low-k wafers by altering aluminum pad/passivation stack to reduce or eliminate imc cracking in post wire bonded dies
20070104029 - Method and computer program for spreading trace segments in an integrated circuit package design
20070104273 - Method for robust inverse telecine
20070098157 - Using code as keys for copy protection
20070099313 - Method of design based process control optimization
20070099581 - Variable loop bandwidth phase locked loop
20070100847 - Methods and structure for sas expander initiating communication to a sas initiator to identify changes in the sas domain
20070101043 - Protocol converter to access ahb slave devices using the mdio protocol
20070101089 - Pseudo pipeline and pseudo pipelined sdram controller
April 2007 - Lsi Logic Corporation patents
20070090888 - Method and/or apparatus for implementing a voltage controlled ring oscillator having a multi-peak detected amplitude control loop
20070091105 - High performance tiling for rram memory
20070091702 - Rram controller built in self test memory
20070091741 - Center error mechanical center adjustment
20070091742 - Ce to rro cancellation for sled control
20070091994 - Method and system of frequency domain equalization
20070093124 - Methods and structure for sas expander optimization of sas wide ports
20070094534 - Rram memory error emulation
20070094621 - Method and system for converting netlist of integrated circuit between libraries
20070094633 - Method and system for mapping netlist of integrated circuit to design
20070087615 - Methods and structure for sas domain transceiver optimization
20070088520 - System and method to synchronize and coordinate parallel, automated fault injection processes against storage area network arrays
20070088928 - Methods and systems for locking in storage controllers
20070088941 - Customization of option rom images
20070088990 - System and method for reduction of rebuild time in raid systems through implementation of striped hot spare drives
20070083703 - Load balancing of disk drives
20070083706 - System and method for coercion of disk drive size for use in a raid volume
20070083834 - Method for sram bitmap verification
20070083839 - On-the-fly rtl instructor for advanced dft and design closure
20070079189 - Method and system for generating a global test plan and identifying test requirements in a storage system environment
20070079266 - Method and computer program for analysis of an integrated circuit design to identify and resolve a problematic structure characterized by multiple rule violations using a design closure knowledge base and a physical design database
20070079269 - Method for performing design rule check of integrated circuit
20070079273 - Method and computer program for incremental placement and routing with nested shells
20070079274 - Method and computer program for detailed routing of an integrated circuit design with multiple routing rules and net constraints
20070079277 - Method and system for analyzing the quality of an opc mask
March 2007 - Lsi Logic Corporation patents
20070050745 - Timing violation debugging inside place and route tool
February 2007 - Lsi Logic Corporation patents
20070040284 - Two layer substrate ball grid array design
20070040840 - Method and/or apparatus for video data storage
20070044053 - Multimode delay analyzer
20070044056 - Macro block placement by pin connectivity
20070044058 - Enabling efficient design reuse in platform asics
20070044059 - Ip placement validation
20070036043 - Safe recovery in dvd recordable/rewritable realtime recording
20070036513 - Dvd efm modulation architecture using two passes to reduce circuit size
20070030584 - Compressed domain commercial detect/skip
20070030898 - Performance adaptive video encoding with concurrent decoding
20070030901 - H.264 to vc-1 and vc-1 to h.264 transcoding
20070030902 - Method and apparatus for vc-1 to mpeg-2 video transcoding
20070030903 - Method and apparatus for h.264 to mpeg-2 video transcoding
20070030904 - Method and apparatus for mpeg-2 to h.264 video transcoding
20070030905 - Video bitstream transcoding method and apparatus
20070030906 - Method and apparatus for mpeg-2 to vc-1 video transcoding
20070030996 - Method and/or apparatus for video watermarking and steganography using simulated film grain
20070033337 - Configurable high-speed memory interface subsystem
20070033557 - Method for creating constraints for integrated circuit design closure
20070023930 - High speed interface design
20070025482 - Flexible sampling-rate encoder
20070028022 - Apparatus and methods for a static mux-based priority encoder
20070028041 - Extended failure analysis in raid environments
20070028042 - Methods and structure for improved import/export of raid level 6 volumes
20070028043 - Method for creating a large-scale storage array system out of multiple mid-range storage arrays
20070028044 - Methods and structure for improved import/export of raid level 6 volumes
20070028196 - Resource estimation for design planning
20070028199 - Delay computation speed up and incrementality
January 2007 - Lsi Logic Corporation patents
20070018669 - Testing with high speed pulse generator
20070013006 - Apparatus and method of manufacture for integrated circuit and cmos device including epitaxially grown dielectric on silicon carbide
20070013068 - Integrated circuit package and method with an electrical component embedded in a substrate via
20070013695 - Digitally obtaining contours of fabricated polygons
20070015297 - Failure analysis vehicle for yield enhancement with self test at speed burnin capability for reliability testing
20070008791 - Dqs strobe centering (data eye training) method
20070009181 - Efficient and high speed 2d data transpose engine for soc application
20070011642 - Application specific configurable logic ip
20070002642 - Method and/or apparatus for training dqs strobe gating
20070002991 - Adaptive elasticity fifo
20070004191 - Novel techniques for precision pattern transfer of carbon nanotubes from photo mask to wafers
20070005116 - Implantable, fully integrated and high performance semiconductor device for retinal prostheses
December 2006 - Lsi Logic Corporation patents
20060290391 - Integrated clock generator with programmable spread spectrum using standard pll circuitry
20060290694 - Local reconstruction of a tetrahedral grid
20060291302 - Programmable data strobe enable architecture for ddr memory applications
20060291467 - System & method for fabric storage utilizing multicast with distributed intelligence
20060292716 - Use selective growth metallization to improve electrical connection between carbon nanotubes and electrodes
20060294482 - Method and computer program for estimating speed-up and slow-down net delays for an integrated circuit design
20060284310 - Offset via on pad
20060284658 - Rise and fall balancing circuit for tri-state inverters
20060284665 - High-speed tdf testing on low cost testers using on-chip pulse generators and dual ate references for rapidchip and asic devices
20060285010 - Systems and methods for deinterlacing video signals
20060288175 - Feedback programmable data strobe enable architecture for ddr memory applications
20060278902 - Nano structure electrode design
20060279005 - Techniques for forming passive devices during semiconductor back-end processing
20060279326 - Method of interconnect for multi-slot metal-mask programmable relocatable function placed in an i/o region
20060280104 - Demodulation of a focusing error signal during a focus search for a lens focusing control in an optical disc system
20060281256 - Self-aligned cell integration scheme
20060281287 - Method of aligning deposited nanotubes onto an etched feature using a spacer
20060282728 - Methods for using checksums in x-tolerant test response compaction in scan-based testing of integrated circuits
20060282808 - Automatic generation of correct minimal clocking constraints for a semiconductor product
20060273800 - Simulated battery logic testing device
20060277329 - Method for reducing latency
November 2006 - Lsi Logic Corporation patents
20060268486 - Automatic placement based esd protection insertion
20060268723 - Selective test point for high speed serdes cores in semiconductor design
20060268724 - Using open vera assertions to verify designs
20060268941 - Adaptive method for training a source synchronous parallel receiver
20060271901 - Mixed-signal functions using r-cells
20060262513 - Electromagnetic interference shield for data storage systems
20060263933 - Use of configurable mixed-signal building block functions to accomplish custom functions
20060264053 - Method of aligning nanotubes and wires with an etched feature
20060258023 - Method and system for improving integrated circuit manufacturing yield
20060258122 - Nanotube fuse structure
20060259278 - Systems and methods for analyzing data of a sas/sata device
20060259841 - Relocatable built-in self test (bist) elements for relocatable mixed-signal elements
20060259892 - R-cells containing cdm clamps
20060249302 - Ball grid array assignment
20060252143 - High resolution semiconductor bio-chip with configuration sensing flexibility
20060253744 - Fibre selective control switch system
20060253751 - Method and system for improving quality of a circuit through non-functional test pattern identification
20060253753 - System and method for improving transition delay fault coverage in delay fault tests through use of an enhanced scan flip-flop
20060253754 - System and method for improving transition delay fault coverage in delay fault tests through use of transition launch flip-flop
20060253825 - Relocatable mixed-signal functions
20060244482 - Configurable i/os for multi-chip modules
20060244868 - Method for composite video artifacts reduction
20060245126 - Cdm esd event protection in application circuits
20060245127 - Cdm esd event simulation and remediation thereof in application circuits
20060248418 - Scan test expansion module
20060248491 - I /o planning with lock and insertion features
October 2006 - Lsi Logic Corporation patents
20060237799 - Carbon nanotube memory cells having flat bottom electrode contact surface
20060239052 - Distributed relocatable voltage regulator
20060239262 - Connection memory for tributary time-space switches
20060239341 - Continuous-time decision feedback equalizer
20060242515 - Systematic scan reconfiguration
20060242522 - Test vehicle data analysis
20060236123 - Security application using silicon fingerprint identification
20060236169 - Method and circuit for parametric testing of integrated circuits with an exclusive-or logic tree
20060236176 - Segmented addressable scan architecture and method for implementing scan-based testing of integrated circuits
20060226530 - Advanced standard cell power connection
20060226847 - Defect analysis using a yield vehicle
20060227866 - Method for specification of quantized coefficient limit
20060227867 - Method for coefficient bitdepth limitation, encoder and bitstream generation apparatus
20060230125 - System and method for sas phy dynamic configuration
20060230373 - Intelligent timing analysis and constraint generation gui
20060219572 - Abrasive electrolyte
20060221789 - Control of stepper motor in an optical disc
20060223341 - Ball assignment system
20060224847 - Memory interface architecture for maximizing access timing margin
September 2006 - Lsi Logic Corporation patents
20060209958 - Method and/or apparatus for implementing global motion compensation in a video system
20060202303 - Package configuration and manufacturing method enabling the addition of decoupling capacitors to standard package designs
20060202307 - Bipolar transistors having controllable temperature coefficient of current gain
20060203556 - Flash memory controller utilizing multiple voltages and a method of use
20060205203 - Dual layer barrier film techniques to prevent resist poisoning
20060206843 - Probabilistic noise analysis
20060197193 - Superconductor wires for back end interconnects
20060199366 - Reduced dry etching lag
20060200491 - Remote status and control of storage devices
20060200595 - Variable length command pull with contiguous sequential layout
20060200787 - Method for tracing paths within a circuit
20060200788 - Method for describing and deploying design platform sets
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This listing is an abstract for educational and research purposes is only meant as a recent sample of applications filed, not a comprehensive history. Freshpatents.com is not affiliated or associated with Lsi Logic Corporation in any way and there may be associated servicemarks. This data is also published to the public by the USPTO and available for free on their website. Note that there may be alternative spellings for Lsi Logic Corporation with additional patents listed. Browse our Agent directory for other possible listings.
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