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Low voltage charge pump

Low voltage charge pump description/claims

The present invention relates to charge pump circuits.

Charge pump circuits are frequently used in a semiconductor integrated circuit to provide an internal voltage that is higher than an external voltage provided to the semiconductor integrated circuit from an external power supply, such as a battery. Charge pump circuits are also used to provide a voltage of reverse polarity. Charge pump circuits are particularly useful in FLASH and EEPROM non-volatile memories, but are gaining more and more acceptance in analog circuits in order to increase dynamic range and to simplify circuit design.

FIG. 1 illustrates a conventional Dickson charge pump 10 which uses multiple stages of switched-capacitor circuits. Each of the stages includes a capacitor and a diode-connected NMOS transistor. A first Dickson charge pump stage includes an NMOS transistor ND1 and a capacitor C1. A second Dickson charge pump stage includes an NMOS transistor ND2 and a capacitor C2. A third Dickson charge pump stage includes an NMOS transistor ND3 and a capacitor C3. A fourth Dickson charge pump stage includes an NMOS transistor ND4 and a capacitor C4. A fifth Dickson charge pump stage includes an NMOS transistor ND5 and a capacitor C5. The NMOS transistors ND1, ND2, ND3, ND4, ND5 each have their bulk or substrate connected to ground, their drain and gate connected together to a stage capacitor, and their source connected to the capacitor of the next stage. Two oppositely phased clock signals, ΦDA and ΦB are used for pumping charge from stage to stage. The maximum gain per stage of the Dickson charge pump 10 is (VDD-VT), where VT is the threshold voltage of an NMOS device. For n stages, the gain of a conventional Dickson charge pump is n(VDD-VT). The gain is thus reduced by n times the VT threshold voltage.

For some applications, the conventional Dickson charge pump 10 has a number of drawbacks. For instance, the number of stages that can be cascaded is limited by the amount of the voltage drop increase between the source and the bulk of an NMOS device resulting in a dramatic VT increase on the last stages. Another significant drawback is that high voltage transistors with thick oxide layers are necessary to sustain a large voltage drop between gate and bulk in a reliable way. This makes it difficult to design conventional Dickson charge pumps using thin oxide, low voltage standard devices which can sustain a maximum drop of only VDD.

One embodiment of a charge pump stage includes a NMOS section and a PMOS section. The NMOS section includes: a first NMOS transistor coupled between an input node and an intermediate node; a second NMOS transistor coupled between a gate of the first NMOS transistor and the input node and with a gate coupled to the intermediate node for refreshing a voltage at the gate of the first NMOS transistor. A first transfer capacitor is coupled between the input node and a first clock input terminal and is configured to receive a first clock input signal. A first coupling capacitor is coupled between the gate of the first NMOS transistor and a boost clock signal terminal that is configured to receive a boost clock signal. The PMOS section includes: a first PMOS transistor coupled between the intermediate node and an output node, a second PMOS transistor coupled between a gate of the first PMOS transistor and the output node with a gate coupled to the intermediate node for refreshing a voltage at the PMOS first gate of the first PMOS transistor. A second transfer capacitor is coupled between the output node and a second inverted clock input terminal and configured to receive an inverted first clock signal. A second coupling capacitor is coupled between the gate of the first PMOS transistor and an inverted boost clock signal terminal that is configured to receive an inverted boost clock signal. A stabilizing capacitor is coupled between the intermediate node and a ground voltage reference terminal.

Another embodiment of a charge pump stage includes a NMOS section that includes: a first NMOS transistor coupled between an input node and an intermediate node, a second NMOS transistor that is coupled between a gate of the first NMOS transistor and the input node and that has a gate coupled to the intermediate node for refreshing a voltage at the first NMOS gate of the first NMOS transistor. A first transfer capacitor is coupled between the input node and a first clock input terminal and is configured to receive a first clock input signal. A first coupling capacitor is coupled between the gate of the first NMOS transistor and a boost clock signal terminal that is configured to receive a boost clock signal while the first clock input signal is active. A PMOS section includes: a first PMOS transistor that is coupled between the intermediate node and an output node, a second PMOS transistor that is coupled between a gate of the first PMOS transistor and the output node and that has a gate coupled to the intermediate node for refreshing a voltage at the first PMOS gate of the first PMOS transistor. A second transfer capacitor is coupled between the output node and a second clock input terminal that is configured to receive a second clock input signal. A second coupling capacitor is coupled between the gate of the first PMOS transistor and an inverted boost clock signal terminal that is configured to receive an inverted boost clock signal while the second clock signal is active. The maximum voltage across the first NMOS transistor, the second NMOS transistor, the first PMOS transistor, and the second PMOS transistor is the VDD supply voltage. A stabilizing capacitor is coupled between the intermediate node and a ground voltage reference terminal.

A multi-stage embodiment of a charge pump includes a plurality of charge pump stages connected in series, each charge pump stage includes a NMOS section and an NMOS section. The NMOS section includes: a first NMOS transistor that is coupled between an input node and an intermediate node, a second NMOS transistor that is coupled between a gate of the first NMOS transistor and the input node and that has a gate coupled to the intermediate node for refreshing the voltage at the first NMOS gate of the first NMOS transistor. A first transfer capacitor is coupled between the input node and a first clock input terminal and is configured to receive a first clock input signal. A first coupling capacitor is coupled between the gate of the first NMOS transistor and a boost clock input terminal that is configured to receive a boost clock signal. The PMOS section includes: a first PMOS transistor that is coupled between the intermediate node and an output node, a second PMOS transistor that is coupled between a gate of the first PMOS transistor and the output node and that has a gate coupled to the intermediate node for refreshing the voltage at the first PMOS gate of the first PMOS transistor. A second transfer capacitor is coupled between the output node and a second inverted clock input terminal and is configured to receive an inverted first clock signal. A second coupling capacitor is coupled between the gate of the first PMOS transistor and an inverted boost clock input terminal and is configured to receive an inverted boost clock signal. The first and the second clock input signals have opposite phases and operate between VDD and 0 volts. The maximum voltage across the first NMOS transistor, the second NMOS transistor, the first PMOS transistor, and the second PMOS transistor is VDD.

FIG. 1 is a simplified circuit diagram of a prior art Dickson charge pump circuit.

FIG. 2 is a circuit diagram of a single stage charge pump.

FIG. 3 is a block diagram of a multi-stage charge pump.

FIG. 4 is a timing chart for the multi-stage charge pump of FIG. 3.

FIG. 5 illustrates Vout as a function of time for a multi-stage charge pump.

FIG. 6 illustrates input and intermediate voltages as functions of time for one stage of a multi-stage charge pump.

FIG. 7 illustrates intermediate and output voltages as functions of time for one stage of a multi-stage charge pump.

• Provisional Patent
• Utility Patent

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