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Low resistance and inductance backside through vias and methods of fabricating sameRelated Patent Categories: Semiconductor Device Manufacturing: Process, Packaging (e.g., With Mounting, Encapsulating, Etc.) Or Treatment Of Packaged Semiconductor, Including Adhesive Bonding StepLow resistance and inductance backside through vias and methods of fabricating same description/claimsThe Patent Description & Claims data below is from USPTO Patent Application 20070190692, Low resistance and inductance backside through vias and methods of fabricating same. Brief Patent Description - Full Patent Description - Patent Application Claims
FIELD OF THE INVENTION [0001] The present invention relates to the field of integrated circuits; more specifically, it relates to backside through vias and methods of fabricating backside through vias for electrical connection to elements of integrated circuits. BACKGROUND OF THE INVENTION [0002] There are many integrated circuit applications where it is desirable to reduce the resistance and inductance of signal lines in circuits normally associated with frontside wire bond pad connections. For example, because of the inductance associated with wire bond pad connections to the emitter of NPN hetero-junction bipolar transistors (HBT), the maximum practical operating frequency of circuits using NPN HBTs in wire bond packages is about 3 GHz even though the transistors are capable of running at higher frequencies. Therefore, there is a need for interconnect structures and methods of fabricating interconnect structures with reduced inductance and resistance for connecting signals to circuit elements of integrated circuits. SUMMARY OF THE INVENTION [0003] A first aspect of the present invention is a method for forming a contact, comprising: forming a dielectric isolation in a substrate, the substrate having a frontside and an opposing backside; forming a first dielectric layer on the frontside of the substrate; forming a trench in the first dielectric layer, the trench aligned over and within a perimeter of the dielectric isolation and extending to the dielectric isolation; extending the trench formed in the first dielectric layer through the dielectric isolation and into the substrate to a depth less than a thickness of the substrate; filling the trench and co-planarizing a top surface of the trench with a top surface of the first dielectric layer to form an electrically conductive through via; and thinning the substrate from the backside of the substrate to expose the through via. [0004] A second aspect of the present invention is the first aspect, further including: forming a device contact opening in the first dielectric layer and simultaneously with the filling the trench and co-planarizing, filling the device contact opening and co-planarizing a top surface of the filled device contact opening with a top surface of the first dielectric layer to form an electrically conductive device contact. [0005] A third aspect of the present invention is the first aspect, further including: before forming the through via, forming a device contact opening in the first dielectric layer, filling the device contact opening and co-planarizing a top surface of the filled device contact opening with a top surface of the first dielectric layer to form an electrically conductive device contact. [0006] A fourth aspect of the present invention is the first aspect, further including: after forming the through via, forming a device contact opening in the first dielectric layer, filling the device contact opening and co-planarizing a top surface of the filled contact opening with a top surface of the first dielectric layer to form an electrically conductive device contact. [0007] A fifth aspect of the present invention is the first aspect, wherein said filling said trench includes: either forming a insulating layer on sidewalls and a bottom of said trench and forming a tungsten layer over said insulating layer, said tungsten layer of sufficient thickness to fill said trench; or forming said tungsten layer on said sidewalls and said bottom of said trench, said tungsten layer of sufficient thickness to fill said trench. [0008] A sixth aspect of the present invention is the first aspect, wherein said filling said trench includes: either forming a insulating layer on sidewalls and a bottom of said trench, forming a conformal polysilicon layer over said insulating layer, and forming a tungsten layer over said polysilicon layer, said tungsten layer of sufficient thickness to fill said trench; or forming said polysilicon layer on said sidewalls and said bottom of said trench; and forming a tungsten layer over said polysilicon layer, said tungsten layer of sufficient thickness to fill said trench. [0009] A seventh aspect of the present invention is the first aspect, wherein said filling said trench includes: either forming a insulating layer on sidewalls and a bottom of said trench; forming a conformal tungsten layer over said insulating layer, and forming an oxide layer over said tungsten layer, said oxide layer of sufficient thickness to fill said trench; or forming a conformal tungsten layer on said sidewalls and said bottom of said trench, and forming an oxide layer over said tungsten layer, said oxide layer of sufficient thickness to fill said trench. [0010] An eighth aspect of the present invention is the first aspect, wherein said filling said trench includes: either forming a insulating layer on sidewalls and a bottom of said trench, forming a conformal polysilicon layer over said insulating layer, forming a conformal tungsten layer over said polysilicon layer, and forming an oxide layer over said tungsten layer, said oxide layer of sufficient thickness to fill said trench; or forming a conformal polysilicon layer on said sidewalls and said bottom of said trench, forming a conformal tungsten layer over said polysilicon layer, and forming an oxide layer over said tungsten layer, said oxide layer of sufficient thickness to fill said trench. [0011] A ninth aspect of the present invention is the first aspect, further including: forming a hetero-junction bipolar transistor in and on said substrate; forming a device contact in the first dielectric layer, the device contact in physical and electrical contact to an emitter of the hetero-junction bipolar transistor; and forming a wire in a second dielectric layer, the second dielectric layer formed over the first dielectric layer and the wire in direct physical and electrical contact with the device contact and the through via. [0012] A tenth aspect of the present invention is the first aspect, wherein the trench extends to and contacts a buried oxide layer in the substrate and the thinning the substrate removes the buried oxide layer. BRIEF DESCRIPTION OF DRAWINGS [0013] The features of the invention are set forth in the appended claims. The invention itself, however, will be best understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings, wherein: [0014] FIGS. 1A through 1E are cross-sectional drawings illustrating fabrication of a backside interconnect structure according to a first embodiment of the present invention; [0015] FIGS. 1F through 1H are cross-sectional drawings illustrating variations of backside interconnect structures according to the first embodiment of the present invention; [0016] FIGS. 2A through 2E are cross-sectional drawings illustrating fabrication of a backside interconnect structure according to a second embodiment of the present invention; [0017] FIGS. 3A1 through 3A5 are cross-sectional drawings illustrating fabrication of a backside interconnect structure according to a first variation of a third embodiment of the present invention; [0018] FIGS. 3B1 through 3B3 are cross-sectional drawings illustrating fabrication of a backside interconnect structure according to a second variation of the third embodiment of the present invention; [0019] FIGS. 3C1 through 3C3 are cross-sectional drawings illustrating fabrication of a backside interconnect structure according to a third variation of the third embodiment of the present invention; [0020] FIGS. 4A1 through 4A3 are cross-sectional drawings illustrating a first method of filling a through via or stud contact of the third embodiment of the present invention; Continue reading about Low resistance and inductance backside through vias and methods of fabricating same... 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