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08/31/06 - USPTO Class 345 |  130 views | #20060192738 | Prev - Next | About this Page  345 rss/xml feed  monitor keywords

Liquid crystal display device and manufacturing method thereof

USPTO Application #: 20060192738
Title: Liquid crystal display device and manufacturing method thereof
Abstract: A liquid crystal display device includes a first substrate, a second substrate, and a liquid crystal supported between the first substrate and the second substrate. A signal line, a pixel electrode, and a thin film transistor are formed on the first substrate and electrically connected to the signal line and the pixel electrode, and a drain driver supplies a gray scale voltage to the pixel electrode. Plural voltage-dividing resistance elements are formed on the first substrate, and supply plural gray scale reference voltages to the drain driver. The plural voltage-dividing resistance elements and the signal line are constructed of a same wiring material. (end of abstract)



Agent: Antonelli, Terry, Stout & Kraus, LLP - Arlington, VA, US
Inventors: Tetsuya Kawamura, Yoshihiro Imajo
USPTO Applicaton #: 20060192738 - Class: 345089000 (USPTO)

Liquid crystal display device and manufacturing method thereof description/claims


The Patent Description & Claims data below is from USPTO Patent Application 20060192738, Liquid crystal display device and manufacturing method thereof.

Brief Patent Description - Full Patent Description - Patent Application Claims
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CROSS REFERENCE TO RELATED APPLICATION

[0001] This application is a continuation of U.S. application Ser. No. 10/253,930, filed Sep. 25, 2002, the contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

[0002] The present invention relates to a liquid crystal display device; and, more particularly, the invention relates to a technique that is effective when applied to a driving circuit of the liquid crystal display device, in a system for transferring a digital signal between driving circuits (drain drivers).

[0003] A liquid crystal display module of the STN (super Twisted Nematic) system or the TFT (Thin film Transistor) system, having a large-sized liquid crystal display panel with a pixel number of e.g., 800.times.480.times.3, or more in a panel capable of producing a color display, is widely used as a display device in a notebook type of personal computer, etc. These liquid crystal display devices have a liquid crystal display panel and a driving circuit for operating the liquid crystal display panel.

[0004] For example, JP-A-6-13724/1994, discloses a method (hereinafter called a digital signal sequential transfer method) in which a digital signal (e.g., display data or a clock signal) is inputted to only the head driving circuit of cascade-connected driving circuits, and then the digital signal is sequentially transferred to the other driving circuits through the interior of the driving circuits in a liquid crystal display device. In the liquid crystal display device described in this publication (JP-A-6-13724/1994), a semiconductor integrated circuit device (IC) constituting the driving circuit is directly mounted on a glass substrate of the liquid crystal display panel.

[0005] FIG. 9 is a block diagram showing the basic construction of a liquid crystal display panel employed in a conventional liquid crystal display device using the digital signal sequential transfer method mentioned above. In the liquid crystal display panel shown in this figure, a timing controller (or a display control device) 110, a plurality of drain drivers 130 and a plurality of gate drivers 140 are respectively mounted on peripheral portions along two sides of a transparent insulating substrate (glass substrate) constituting a TFT substrate of the liquid crystal display panel 100.

[0006] A digital signal (display data, a clock signal, etc.), that is sent from the timing controller 110, and a gray scale reference voltage, that is supplied from a power source circuit, are inputted to the head drain driver 130, and these signals are propagated in respective internal signal line within each drain driver 130 and on respective transmission line paths (a wiring layer on the glass substrate) between the respective drain drivers 130, and are, in this way, inputted to each drain driver 130. The source voltage of each drain driver 130 is supplied from a power source circuit 120 to each drain driver 130 through a flexible printed wiring board (hereinafter simply called an FPC board) 150.

[0007] Similarly, the digital signal (clock signal, etc.) sent from the timing controller 110 is inputted to the head gate driver 140, and this signal is propagated in an internal signal line within each gate driver 140 and a transmission line path between the respective gate drivers 140, and is, in this way, inputted to each gate driver 140. However, on the gate driver side, the source voltage of the gate driver 140, that is supplied from the power source circuit 120, is also supplied to the head gate driver 140, and this voltage is supplied to each gate driver 140 through an internal power source line within each gate driver 140 and a transmission line path between the respective gate drivers 140.

SUMMARY OF THE INVENTION

[0008] The above-referenced power source circuit 120 has a DC-DC converter. Plural output voltages having respectively different voltage levels are generated from an input voltage at a single voltage level by this DC-DC converter, and the plural output voltage are supplied as source voltages of each drain driver 130 and each gate driver 140. Two output voltages generated by the DC-DC converter are divided by a resistance voltage-dividing circuit, so that plural gray scale reference voltages are generated. These gray scale reference voltages are supplied to the respective drain drivers 130.

[0009] In the design of such a system, there is a possibility that the specification of the source voltage to be supplied to each drain driver 130 and each gate driver 140 will be changed between the time of the product design starting stage and the time of the product forwarding stage. Further, there is the situation in which the specification of the number of gray scale reference voltages supplied to the respective drain drivers 130 will need to be changed in response to, e.g., intended use, customer request, etc. However, when the specification of the power source circuit 120 is changed in response to such situations, problems exist in that the period until the forwarding of the liquid crystal display module to the customer is lengthened, and the cost of the power source circuit 120 is increased, so that the overall cost of the liquid crystal display module is increased.

[0010] Thus, in the conventional liquid crystal display device, for example, problems exist when it is necessary to change the specification of the power source circuit in accordance with a design change in the liquid crystal display panel, etc., with the result that the period until the forwarding of the liquid crystal display device to the customer is long and the cost is further increased.

[0011] To solve the above-described problems, an object of the present invention is to provide a technique that makes it possible to shorten the period until the product is ready for forwarding, and to reduce the cost involving various kinds of design changes, in comparison with the conventional case in the liquid crystal display device.

[0012] The above and other objects and novel features of the present invention will become more apparent from the following description and the accompanying drawings.

[0013] A summary of typical features of the invention disclosed in this application will be briefly described as follows.

[0014] Namely, the present invention resides in a liquid crystal display device comprising a liquid crystal display panel having a liquid crystal material supported between first and second substrates; plural semiconductor chips for operating a plurality of liquid crystal display elements disposed in a matrix array in said panel; and a power source circuit; wherein said first substrate has a resistance voltage-dividing circuit mounted on a peripheral portion at one side thereof, and said resistance voltage-dividing circuit operates to divide the voltage supplied from said power source circuit and to supply the divided voltage to each of said semiconductor chips.

[0015] In a preferred embodiment, the present invention is characterized in that said plural semiconductor chips are mounted at least on peripheral portions at two adjacent sides of said first substrate.

[0016] In a preferred embodiment, the present invention is also characterized in that said plural semiconductor chips are arranged as semiconductor chips of a first group mounted on a peripheral portion of a first side of said first substrate, and semiconductor chips of a second group mounted on a peripheral portion of a second side, adjacent to said first side, of said first substrate; and said resistance voltage-dividing circuit operates to divide the voltage supplied from said power source circuit, to generate plural gray scale reference voltages, and to supply the plural gray scale reference voltages to the semiconductor chips of said first group.

[0017] In a preferred embodiment, the present invention is also characterized in that said plural semiconductor chips are disposed as semiconductor chips of a first group arranged on a first side of said first substrate, and semiconductor chips of a second group arranged on a second side, adjacent to said first side, of said first substrate; and said resistance voltage dividing circuit operates to divide the voltage supplied from said power source circuit, to generate plural gray scale reference voltages, and to supply the plural gray scale reference voltages to the semiconductor chips of said first group.

[0018] The present invention also resides in a method of manufacture of a liquid crystal display device comprising a liquid crystal display panel having a liquid crystal material supported between first and second substrates; plural semiconductor chips for operating a plurality of liquid crystal display elements disposed in a matrix array in said panel; and a power source circuit; wherein said first substrate has a resistance voltage-dividing circuit mounted on a peripheral portion at one side thereof; and said resistance voltage-dividing circuit operates to divide the voltage supplied from said power source circuit and to supply the divided voltage to each of said semiconductor chips; the manufacturing method comprising a first process for forming plural voltage-dividing resistance elements constituting said resistance voltage-dividing circuit on said first substrate; and a second process for adjusting at least one resistance value among the plural resistance elements formed in said first process.

[0019] In a preferred mode, the present invention is also characterized in that said first process includes a process for constructing at least one of said plural voltage-dividing resistance elements by use of a parallel resistance circuit having plural resistance elements electrically connected in parallel; and said second process is a process for retaining at least one of said plural resistance elements constituting said parallel resistance circuit, and separating the other resistance elements from said at least one resistance element.

[0020] In a preferred mode, the present invention is also characterized in that said first process includes a process for constructing at least one of said plural voltage-dividing resistance elements by use of a first resistance element and plural resistance elements arranged near said first resistance element; and said second process is a process for electrically connecting at least one of said plural resistance elements in parallel to said first resistance element.

[0021] In a preferred mode, the present invention is also characterized in that said first process includes a process for constructing at least one of said plural voltage-dividing resistance elements by use of a resistance element and an element for short-circuiting, having one end connected to one end of said resistance element and also having the other end in an open state; and said second process is a process for electrically connecting the other end of said element for short-circuiting to an arbitrary position of said resistance element.

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