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  Light-emitting diode and method for manufacturing same, integrated light-emitting diode and method for manufacturing same, method for growing a nitride-based iii-v group compound semiconductor, substrate for growing a nitride-based iii-v group compound seUSPTO Application #: 20070085093Title: Light-emitting diode and method for manufacturing same, integrated light-emitting diode and method for manufacturing same, method for growing a nitride-based iii-v group compound semiconductor, substrate for growing a nitride-based iii-v group compound se Abstract: A method for manufacturing a light-emitting diode, which includes the steps of: providing a substrate having a plurality of protruded portions on one main surface thereof wherein the protruded portion is made of a material different in type from that of the substrate and growing a first nitride-based III-V Group compound semiconductor layer on each recess portion of the substrate through a state of making a triangle in section wherein a bottom surface of the recess portion becomes a base of the triangle; laterally growing a second nitride-based III-V Group compound semiconductor layer on the substrate from the first nitride-based III-V Group compound semiconductor layer; and successively growing, on the second nitride-based III-V Group compound semiconductor layer, a third nitride-based III-V Group compound semiconductor layer of a first conduction type, an active layer, and a fourth nitride-based III-V compound semiconductor layer of a second conduction type. (end of abstract) Agent: Sonnenschein Nath & Rosenthal LLP - Chicago, IL, US Inventors: Akira Ohmae, Michinori Shiomi, Noriyuki Futagawa, Takaaki Ami, Takao Miyajima, Yuuji Hiramatsu, Izuho Hatada, Nobukata Okano, Shigetaka Tomiya, Katsunori Yanashima, Tomonori Hino, Hironobu Narui USPTO Applicaton #: 20070085093 - Class: 257089000 (USPTO) Related Patent Categories: Active Solid-state Devices (e.g., Transistors, Solid-state Diodes), Incoherent Light Emitter Structure, Plural Light Emitting Devices (e.g., Matrix, 7-segment Array), Multi-color Emission The Patent Description & Claims data below is from USPTO Patent Application 20070085093. Brief Patent Description - Full Patent Description - Patent Application Claims
CROSS REFERENCES TO RELATED APPLICATIONS [0001] The present application contains subject matter related to Japanese Patent Application JP 2005-275504 filed with the Japanese Patent Office on Sep. 22, 2005, and Japanese Patent Application JP 2006-215342 filed with the Japanese Patent Office on Aug. 8, 2006, the entire contents of which being incorporated herein by reference. BACKGROUND OF THE INVENTION [0002] 1. Field of the Invention [0003] This invention relates to a light-emitting diode and a method for manufacturing same, an integrated light-emitting diode and a method for making same, a method for growing a nitride-based III-V Group compound semiconductor, a substrate for growing a nitride-based III-V Group compound semiconductor, a light source cell unit, a light-emitting diode backlight, a light-emitting diode illuminating device, a light emitting diode display, an electronic instrument, and an electronic device and a method for manufacturing same. The invention is suited for application, for example, to a light-emitting diode using a nitride-based III-V Group compound semiconductor and also to various types of instruments or devices using the light-emitting diode. [0004] 2. Description of the Related Art [0005] In case where a GaN semiconductor is epitaxially grown on a hetero-substrate such as a sapphire substrate, crystal defects, especially, threading dislocations, occur in high density owing to the great difference in lattice constant or coefficient of thermal expansion therebetween. [0006] To avoid this problem, a dislocation density reducing technique based on selective lateral growth has been hitherto in wide use. In this technique, a GaN semiconductor is epitaxially grown on a sapphire substrate or the like, after which the substrate is removed from a crystal growth device. A growth mask made of a SiO.sub.2 film or the like is formed on the GaN semiconductor layer, and the substrate is returned to the crystal growth device, followed by epitaxially growing a GaN semiconductor once more by use of the growth mask. [0007] According to this technique, although the dislocation density in the upper GaN semiconductor layer can be reduced, the epitaxial growth is needed twice, resulting in high costs. [0008] To cope with this, there has been proposed a method, in which a hetero-substrate is subjected to patterned indentation and a GaN semiconductor is epitaxially grown on the indented substrate (e.g. see Mitsubishi Cable Industries Review No. 98, October, 2001, entitled "Development of High Output UV LED Using an LEPS Technique" and Japanese Patent Laid-open Nos. 2004-6931 and 2004-6937). The outline of this method is shown in FIGS. 77A to 77C. According to this method, as shown in FIG. 77A, patterned indentation is made in one main surface of the c face of a sapphire substrate 101. A recessed portion is indicated by reference numeral 101a and a protruded portion is indicated by reference numeral 101b. These recessed portions 101a and protruded portions 101b, respectively, extend along a <1-100> direction of the sapphire substrate 101. Next, a GaN semiconductor layer 102 is formed over the sapphire substrate 101 via the steps shown in FIGS. 77B and 77C. In FIG. 77C, the dotted line indicates a growth interface in the course of the growth. As is particularly shown in FIG. 77C, it is characteristically observed that the recessed portion 101a is unfavorably formed with a space 103 between the sapphire substrate 101 and the GaN semiconductor 102. The distribution of crystal defects in the GaN semiconductor layer 102 grown by the method is schematically shown in FIG. 78. As shown in FIG. 78, threading dislocations 104 occur at a portion over the protruded portion 101b of the GaN semiconductor layer 102 in a direction vertical to the interface with an upper surface of the protruded portion 101b, thereby forming a high defect density region 105. On the other hand, an area or portion above the recessed portion 101a becomes a low defect density region 106 at a portion between the high defect density regions 105. [0009] It will be noted that although, in FIG. 77C, the GaN semiconductor layer 102 beneath the space 103 formed within the recessed portion 101a of the sapphire substrate 101 is buried in the form of a rectangle, the buried form may be triangular in some case. In the latter case, the GaN semiconductor layer 102 buried inside the recessed portion 101a is in contact with the GaN semiconductor layer 102 laterally grown from the protruded portion 101b, with the possibility that a space is formed, like the rectangular form. [0010] For reference, there is shown in FIGS. 79A to 79D how a GaN semiconductor layer 102 is grown in case where the direction of extension of the recessed portions 101a and the protruded portions 101b is a <11-20> direction of intersecting at right angles with a <1-100> direction of the sapphire substrate 101. [0011] FIGS. 80A to 80F schematically show another conventional growth method (Refer to, for example, Japanese Patent Laid-open No. 2003-31441). In this method, as shown in FIG. 80A, a sapphire substrate 101 subjected to patterned indentation is used, and a GaN semiconductor layer 102 is grown thereon through the steps shown in FIGS. 80B to 80F. It is stated that according to the method, the GaN semiconductor layer 102 can be grown without formation of a space in relation with the sapphire substrate 101. [0012] A further growth method has been proposed in which protruded portions are formed on a substrate using a material different from that of the substrate and a nitride III-V Group compound semiconductor starts to be grown from a recess portion between the protruded portions (see, for example, Japanese patent Laid-open No. 2003-324069 and Japanese Patent No. 2830814). However, the manner of the growth in this method greatly differs from that of the present invention. [0013] Only for reference, main crystal faces and crystal orientations of sapphire are shown in FIGS. 81A and 81B. SUMMARY OF THE INVENTION [0014] With the conventional method illustrated with respect to FIGS. 77A to 77C, the formation of the space 103 between the sapphire substrate 101 and the GaN semiconductor layer 102 is as stated hereinabove. According to the results of a test made by us, where a light-emitting diode structure in which a GaN semiconductor layer is formed on the GaN semiconductor layer 102 is formed, there is left a problem that the luminous efficiency of the light-emitting diode is low. This is considered for the reason that light generated from an active layer in the course of operation of the light-emitting diode is repeatedly reflected at the inside of the space 103 and is eventually absorbed, thereby worsening a light extraction efficiency. [0015] On the other hand, with the conventional growth method illustrated with respect to 80A to 80F, although it is stated that the space 103 is not formed between the sapphire substrate 101 and the GaN semiconductor layer 102, it is considered that a difficulty is involved in reducing the dislocation density in the GaN semiconductor layer 102 to such a level as that of the conventional growth method shown in FIGS. 77A to 77C. For this, where a light-emitting diode structure in which a GaN semiconductor layer is grown on the GaN semiconductor layer 102 having this high dislocation density is formed, the dislocation density of these GaN semiconductor layers becomes high, thereby inviting a lowering of luminous efficiency. [0016] Further, in either of the conventional growth methods illustrated in FIGS. 77A to 77C and 80A to 80F, dry etching is usually used to subject the surface of the sapphire substrate 101 to patterned indentation, but the sapphire substrate 101 is very unlikely to undergo dry etching, thus not only taking a long time for the etching, but also being low in processing accuracy. [0017] Accordingly, it is desirable to provide a light-emitting diode and a method for manufacturing such a diode in which a light extraction efficiency is remarkably improved owing to the absence of such a space as set out hereinabove, a nitride-based III-V Group compound semiconductor layer constituting a light-emitting diode is significantly improved in crystallinity to provide a very high luminous efficiency, and the diode can be manufactured at low costs by a single run of epitaxial growth, with the ease in processing of a substrate to provide a protrusion and recess pattern thereon. [0018] It is further desirable to provide an integrated light-emitting diode and a method for manufacturing same in a manner as set out in the first desire, a method for growing a nitride-based III-V Group compound semiconductor conveniently used for the manufacture of such a light-emitting diode and integrated light-emitting diode as mentioned above, and a substrate useful for the growth of such a nitride-based III-V Group compound semiconductor. [0019] It is still further desirable to provide a high-performance light source cell unit, light-emitting diode backlight, light-emitting diode illuminating device, light-emitting diode display and electronic device, each using such a diode as mentioned above. [0020] It is yet further desirable to provide electronic devices such as a light-emitting diode, a semiconductor laser, a transistor and the like and a method for manufacturing such devices, in which characteristic properties are very good owing to the absence of such a space as set out hereinbefore and an remarkable improvement of crystallinity of a layer material constituting a device structure, such electronic devices can be manufactured at low costs by a single run of epitaxial growth, and patterned indentation of a substrate is simple. [0021] In order to achieve those desires, according to a first embodiment of the invention, there is provided a method for manufacturing a light-emitting diode. The method includes a providing step, laterally growing step, and successively growing step. The providing step provides a substrate having a plurality of protruded portions on one main surface thereof, in which the protruded portion is made of a material different in type from that of the substrate, and grows a first nitride-based III-V Group compound semiconductor layer on each recess portion of the substrate through a state of making a triangle in section wherein a bottom surface of the recess portion becomes a base of the triangle. The laterally growing step grows a second nitride-based III-V Group compound semiconductor layer on the substrate from the first nitride-based III-V Group compound semiconductor layer. The successively growing step grows a third nitride-based III-V Group compound semiconductor layer of a first conduction type, an active layer, and a fourth nitride-based III-V compound semiconductor layer of a second conduction type on the second nitride-based III-V Group compound semiconductor layer. Continue reading... Full patent description for Light-emitting diode and method for manufacturing same, integrated light-emitting diode and method for manufacturing same, method for growing a nitride-based iii-v group compound semiconductor, substrate for growing a nitride-based iii-v group compound se Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Light-emitting diode and method for manufacturing same, integrated light-emitting diode and method for manufacturing same, method for growing a nitride-based iii-v group compound semiconductor, substrate for growing a nitride-based iii-v group compound se patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. 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